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Sat, 29 Aug 2026 02:57:37 +0000 From: Changhuang Liang To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Emil Renner Berthing , Paul Walmsley , Albert Ou , Palmer Dabbelt , Alexandre Ghiti , Philipp Zabel , Bartosz Golaszewski Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Lianfeng Ouyang , Changhuang Liang Subject: [PATCH v6 03/21] dt-bindings: pinctrl: Add starfive,jhb100-sys0-pinctrl Date: Fri, 28 Aug 2026 19:57:02 -0700 Message-Id: <20260829025720.23915-4-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260829025720.23915-1-changhuang.liang@starfivetech.com> References: <20260829025720.23915-1-changhuang.liang@starfivetech.com> Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: NT0PR01CA0020.CHNPR01.prod.partner.outlook.cn (10.2.8.16) To ZQ4PR01MB1202.CHNPR01.prod.partner.outlook.cn (10.2.3.102) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: ZQ4PR01MB1202:EE_|ZQ4PR01MB1153:EE_ X-MS-Office365-Filtering-Correlation-Id: 92caf5a8-232d-4f5d-e494-08df05794874 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|1800799024|23010399003|7416014|376014|52116014|3023799007|18002099003|22082099003|56012099006|6133799003|10067099003|921020|38350700014; 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On the StarFive JHB100 SoC, every 32 GPIOs correspond to one register address. Therefore, under this model, every 32 GPIOs can be regarded as one GPIO instance. In this case, the following new approach can be used to represent this model: gpios = <&gpio [instance] offset flags>; gpio-ranges = <&pinctrl [gpio_instance] gpio_offset pin_offset count>; At the same time, this model also reduces the /32 and %32 operations in the driver. Signed-off-by: Changhuang Liang --- .../pinctrl/starfive,jhb100-sys0-pinctrl.yaml | 164 ++++++++++++++++++ .../pinctrl/starfive,jhb100-pinctrl.h | 17 ++ 2 files changed, 181 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys0-pinctrl.yaml create mode 100644 include/dt-bindings/pinctrl/starfive,jhb100-pinctrl.h diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys0-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys0-pinctrl.yaml new file mode 100644 index 000000000000..7df1a1f39f14 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys0-pinctrl.yaml @@ -0,0 +1,164 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/starfive,jhb100-sys0-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JHB100 System-0 Pin Controller + +description: | + Pinctrl bindings for JHB100 RISC-V SoC from StarFive Technology Ltd. + + The JHB100 SoC has 13 pinctrl domains - sys0, sys0h, sys1, sys2, per0, per1, + per2, per2pok, per3, adc0, adc1, emmc, and vga. + This document provides an overview of the "sys0" pinctrl domain. + + The "sys0" domain has a pin controller which provides + - function selection for GPIO pads. + - GPIO pad configuration. + - GPIO interrupt handling. + + In the SYS0 Pin Controller, there are 4 multi-function GPIO_PADs. Each of + them can be multiplexed to different hardware blocks through function + selection and each iopad has a maximum of up to 2 functions - 0 and 1. + Function 0 is the default function which is generally the GPIO function + (or occasionally, it can be a peripheral signal). + Function 1 is the alternate function or peripheral signal that can be + routed to the iopad. The function selection is carried out by writing + the function number to the iopad function select register. + + Each iopad is configurable with parameters such as input-enable, internal + pull-up/pull-down bias, drive strength, schmitt trigger, slew rate, input + debounce nanoseconds. + +maintainers: + - Changhuang Liang + +properties: + compatible: + items: + - const: starfive,jhb100-sys0-pinctrl + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 3 + + gpio-controller: true + + '#gpio-cells': + const: 3 + + gpio-ranges: true + + gpio-line-names: true + +patternProperties: + '-grp$': + type: object + additionalProperties: false + patternProperties: + '-pins$': + type: object + description: | + A pinctrl node should contain at least one subnode representing the + pinctrl groups available in the domain. Each subnode will list the + pins it needs, and how they should be configured, with regard to + function selection, bias, input enable/disable, input schmitt + trigger enable/disable, slew-rate, input debounce and + drive-strength. + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml + - $ref: /schemas/pinctrl/pinmux-node.yaml + additionalProperties: false + + properties: + pins: + description: + The list of IOs that properties in the pincfg node apply to. + + function: + description: + A string containing the name of the function to mux for these + pins. + enum: [ auxpwrgood, gpio, hbled, pe2rst_out ] + + bias-disable: true + + bias-pull-down: + type: boolean + + bias-pull-up: + type: boolean + + drive-strength: + enum: [ 2, 4, 8, 12 ] + + drive-strength-microamp: + enum: [ 2000, 4000, 8000, 12000 ] + + input-debounce-ns: + minimum: 0 + maximum: 10485680 + description: + Debounce time in nanoseconds. The hardware counts in 80 ns + stages with a 17-bit counter, so the maximum is 10485680 ns. + + input-disable: true + + input-enable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + slew-rate: + enum: [ 0, 1 ] + default: 0 + description: | + 0: slow + 1: fast + +required: + - compatible + - reg + - resets + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + pinctrl_sys0: pinctrl@13080000 { + compatible = "starfive,jhb100-sys0-pinctrl"; + reg = <0x0 0x13080000 0x0 0x800>; + resets = <&sys0crg 2>; + interrupts = <56>; + interrupt-controller; + #interrupt-cells = <3>; + gpio-controller; + #gpio-cells = <3>; + gpio-ranges = <&pinctrl_sys0 0 0 0 4>; + }; + }; diff --git a/include/dt-bindings/pinctrl/starfive,jhb100-pinctrl.h b/include/dt-bindings/pinctrl/starfive,jhb100-pinctrl.h new file mode 100644 index 000000000000..6d8f5516a178 --- /dev/null +++ b/include/dt-bindings/pinctrl/starfive,jhb100-pinctrl.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * + * Author: Changhuang Liang + */ + +#ifndef __DT_BINDINGS_PINCTRL_STARFIVE_JHB100_H__ +#define __DT_BINDINGS_PINCTRL_STARFIVE_JHB100_H__ + +/* sys0 pad numbers */ +#define PADNUM_SYS0_GPIO_A0 0 +#define PADNUM_SYS0_GPIO_A1 1 +#define PADNUM_SYS0_GPIO_A2 2 +#define PADNUM_SYS0_GPIO_A3 3 + +#endif -- 2.25.1