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From: Yu Jin <lambda.jinyu@gmail.com>
To: linux-riscv@lists.infradead.org
Cc: Albert Ou <aou@eecs.berkeley.edu>,
	Alexandre Ghiti <alex@ghiti.fr>, Jonathan Corbet <corbet@lwn.net>,
	linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <pjw@kernel.org>,
	Randy Dunlap <rdunlap@infradead.org>,
	Shuah Khan <skhan@linuxfoundation.org>,
	Yu Jin <lambda.jinyu@gmail.com>
Subject: [RFC PATCH 0/2] riscv: document the Sv32 virtual memory layout
Date: Mon, 31 Aug 2026 00:12:03 +0800	[thread overview]
Message-ID: <20260830161205.80162-1-lambda.jinyu@gmail.com> (raw)

The RISC-V virtual memory layout documentation describes the 64-bit
paging modes but has left the Sv32 section as a TODO. The layout is
already defined by the RV32 page-table macros and can be observed in the
boot-time layout printed with CONFIG_DEBUG_VM.

RV32 remains relevant to current hardware rather than only legacy
systems. For example, Espressif announced the ESP32-S31 in March 2026 as
a dual-core 32-bit RISC-V microcontroller with MMU support.

This series documents the existing rv32_defconfig layout and corrects a
nearby comment that gives a stale fixed value for RV32 TASK_SIZE. The
implementation is unchanged.

The main point on which I would appreciate feedback is whether this is
the clearest way to present the configuration-dependent part of the
layout. This is my first Linux kernel contribution, so I would also
appreciate guidance on any process or presentation issues.

Tested on QEMU with a kernel based on commit 08dbfad3f504:

  - rv32_defconfig plus CONFIG_DEBUG_VM=y
  - full RV32 kernel and modules build with GCC 13.3.0
  - boot with qemu-system-riscv32 8.2.2 and 512 MB or 4 GB RAM
  - userspace reached using a minimal initramfs
  - runtime layout matched the documented addresses
  - the 4 GB boot exposed 1 GB of managed RAM, matching the current
    direct-map and no-highmem limitations
  - make SPHINXDIRS=arch/riscv htmldocs
  - scripts/checkpatch.pl --strict, no errors or warnings per patch

The boot-time layout was:

  fixmap  : 0x9c800000 - 0x9d000000
  pci io  : 0x9d000000 - 0x9e000000
  vmemmap : 0x9e000000 - 0xa0000000
  vmalloc : 0xa0000000 - 0xc0000000
  lowmem  : 0xc0000000 - 0xdfc00000

Yu Jin (2):
  docs: riscv: document the Sv32 virtual memory layout
  riscv: mm: correct the stale RV32 TASK_SIZE comment

 Documentation/arch/riscv/vm-layout.rst | 28 +++++++++++++++++++++++++-
 arch/riscv/include/asm/pgtable.h       |  6 ++----
 2 files changed, 29 insertions(+), 5 deletions(-)


base-commit: 08dbfad3f5040f5bdb6c529da20d6d4e81fefd72
-- 
2.43.0


             reply	other threads:[~2026-08-30 16:12 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-30 16:12 Yu Jin [this message]
2026-08-30 16:12 ` [RFC PATCH 1/2] docs: " Yu Jin
2026-08-30 16:12 ` [RFC PATCH 2/2] riscv: mm: correct the stale RV32 TASK_SIZE comment Yu Jin

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