From: Krzysztof Kozlowski <krzk@kernel.org>
To: Biju <biju.das.au@gmail.com>
Cc: "Claudiu Beznea" <claudiu.beznea.uj@bp.renesas.com>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
"Manivannan Sadhasivam" <mani@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Geert Uytterhoeven" <geert+renesas@glider.be>,
"Magnus Damm" <magnus.damm@gmail.com>,
"Biju Das" <biju.das.jz@bp.renesas.com>,
"Rob Herring" <robh@kernel.org>,
linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
"Prabhakar Mahadev Lad" <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: Re: [PATCH 1/4] dt-bindings: PCI: renesas,r9a08g045s33-pcie: Document RZ/G3L SoC
Date: Mon, 31 Aug 2026 08:33:52 +0200 [thread overview]
Message-ID: <20260831-neon-responsible-ape-e0cd02@quoll> (raw)
In-Reply-To: <20260825095047.9971-2-biju.das.jz@bp.renesas.com>
On Tue, Aug 25, 2026 at 10:50:40AM +0100, Biju wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> Extend the existing device tree bindings for Renesas RZ/G3S PCIe
> controller to include support for the RZ/G3L (renesas,r9a08g046-pcie)
> PCIe controller. The RZ/G3L PCIe controller is similar to RZ/G3S but has
> some key differences:
> - Has 3 clocks compared to 2 on other SoCs.
> - Has a different set of reset signals
>
> Add device tree bindings for renesas,r9a08g046-pcie compatible IPs.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> .../bindings/pci/renesas,r9a08g045-pcie.yaml | 33 ++++++++++++++++++-
> 1 file changed, 32 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml b/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml
> index 09d78bd1a577..911b1976bf53 100644
> --- a/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml
> @@ -13,7 +13,7 @@ description: |
> PCIe host controller found in Renesas RZ/G3S and similar SoCs complies
> with PCIe Base Specification 4.0 and supports different link speeds
> depending on the SoC variant:
> - - Gen2 (5 GT/s): RZ/G3S
> + - Gen2 (5 GT/s): RZ/G3{L,S}
> - Gen3 (8 GT/s): RZ/G3E, RZ/V2H(P), RZ/V2N
>
> properties:
> @@ -21,6 +21,7 @@ properties:
> oneOf:
> - enum:
> - renesas,r9a08g045-pcie # RZ/G3S
> + - renesas,r9a08g046-pcie # RZ/G3L
> - renesas,r9a09g047-pcie # RZ/G3E
> - renesas,r9a09g057-pcie # RZ/V2H(P)
> - items:
> @@ -87,14 +88,18 @@ properties:
> interrupt-controller: true
>
> clocks:
> + minItems: 2
> items:
> - description: System clock
> - description: PM control clock or clock for L1 substate handling
> + - description: PM control clock or clock for L1 substate handling
PMU? You list both clocks, but is there any different between them?
>
> clock-names:
> + minItems: 2
> items:
> - const: aclk
> - enum: [pm, pmu]
> + - enum: [pm, pmu]
This should be "const: pmu" in such case.
Best regards,
Krzysztof
next prev parent reply other threads:[~2026-08-31 6:33 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-25 9:50 [PATCH 0/4] Add RZ/G3L PCIe support Biju
2026-08-25 9:50 ` [PATCH 1/4] dt-bindings: PCI: renesas,r9a08g045s33-pcie: Document RZ/G3L SoC Biju
2026-08-31 6:33 ` Krzysztof Kozlowski [this message]
2026-09-03 12:47 ` Biju Das
2026-09-03 12:41 ` Geert Uytterhoeven
2026-08-25 9:50 ` [PATCH 2/4] clk: renesas: r9a08g046: Add PCIe clocks and reset Biju
2026-09-03 12:42 ` Geert Uytterhoeven
2026-08-25 9:50 ` [PATCH 3/4] PCI: rzg3s-host: Add support for RZ/G3L SoC Biju
2026-09-03 12:53 ` Geert Uytterhoeven
2026-08-25 9:50 ` [PATCH 4/4] arm64: dts: renesas: r9a08g046: Add PCIe support Biju
2026-09-03 13:01 ` Geert Uytterhoeven
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