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[86.49.251.7]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4843dcc00a6sm5323903f8f.33.2026.08.31.07.59.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2026 07:59:59 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com Subject: [PATCH v5 09/17] iommu/riscv: Report cache coherency capability Date: Mon, 31 Aug 2026 16:59:35 +0200 Message-ID: <20260831145943.313726-10-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260831145943.313726-1-andrew.jones@oss.qualcomm.com> References: <20260831145943.313726-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=W6UIkxWk c=1 sm=1 tr=0 ts=6a9596f1 cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=on9AXyaqQ0RhfYpiXjjEXA==:17 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=Ikd4Dj_1AAAA:8 a=ITBYzW_wA1tX7bdzKc4A:9 a=PEH46H7Ffwr30OY-TuGO:22 X-Proofpoint-ORIG-GUID: DTaDWr7hCDa0sawzT4nOpsl98LDLusO8 X-Proofpoint-GUID: DTaDWr7hCDa0sawzT4nOpsl98LDLusO8 X-Proofpoint-Spam-Info: AW1haW4tMjYwODMxMDEyOSBTYWx0ZWRfXxldQodQRXSvG Ke3brgBPPzf24z9FjrCEiuQyN8Hg55GSxNWTreenCoyCQ59WI4sv0QzuWjHBynDMnSve88h8YrX FWFXmG2JJLKyTv7yD4y1nn3lubEDRrg= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODMxMDEyOSBTYWx0ZWRfXyWd3qMxUyP/I SRZbk8FUenE+UNZL9WHQWj1lNYo7TfIgJmYE3ZAg8jGhFGmncsQZZTxGjl8VAIkPOBUwQYrFwVw Tr6f+6Xl8IFU3/B0KOnvZGed2j+NvFyYF9pHwNiGjIqph1TzYEPjHPAy5ey/AJedljNNoBU3lxP /kvHSjpjsvtG0Pr6RsgZ3UeHaOz0njga9H2tidNbPugZbpuZRuXWiqc7L8dHj+u7XEyt69TEQLH mCHMbixfIr33Q3TDV3VgWgCi8xrMZuY/QudbZDRaoybRkrYLY5Hh27aq6XL2Eno4hkZCgN9jE+7 8Z494lNbDVMWkiJ9Az8gA1MIteLxy/OstAB3Zq3vMzucI9SYqzu0lDB9rgRsTCg9vt56IFunc9C y7ewA74emRVspHO+MI00X2cg3IS6q4khGgYvmwpDkZA5xCkruuCzrlYKLEYphRlKzc5jJfEW5hb e95GCETtr5gMpZgxIjQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-31_05,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 malwarescore=0 suspectscore=0 bulkscore=0 clxscore=1015 phishscore=0 lowpriorityscore=0 priorityscore=1501 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608310129 VFIO and iommufd require IOMMU_CAP_CACHE_COHERENCY because they use IOMMU_CACHE mappings and have no userspace cache-maintenance path. RISC-V page tables preserve physical memory attributes for IOMMU_CACHE mappings. Svpbmt marks mappings without IOMMU_CACHE as non-cacheable, but preserving physical attributes cannot make a noncoherent device path coherent. Report the capability only for devices marked DMA coherent. This limits userspace assignment to paths that can honor cacheable mappings. Signed-off-by: Andrew Jones Reviewed-by: Jason Gunthorpe --- drivers/iommu/riscv/iommu.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index cec3ddd7ab10..e5818ce44515 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -1422,6 +1423,16 @@ static struct iommu_group *riscv_iommu_device_group(struct device *dev) return generic_device_group(dev); } +static bool riscv_iommu_capable(struct device *dev, enum iommu_cap cap) +{ + switch (cap) { + case IOMMU_CAP_CACHE_COHERENCY: + return dev_is_dma_coherent(dev); + default: + return false; + } +} + static int riscv_iommu_of_xlate(struct device *dev, const struct of_phandle_args *args) { return iommu_fwspec_add_ids(dev, args->args, 1); @@ -1483,6 +1494,7 @@ static void riscv_iommu_release_device(struct device *dev) static const struct iommu_ops riscv_iommu_ops = { .of_xlate = riscv_iommu_of_xlate, + .capable = riscv_iommu_capable, .identity_domain = &riscv_iommu_identity_domain, .blocked_domain = &riscv_iommu_blocking_domain, .release_domain = &riscv_iommu_blocking_domain, -- 2.43.0