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[52.52.135.65]) by smtp-relay.gmail.com with ESMTPS id ada2fe7eead31-785f842fd8bsm120358137.20.2026.08.31.09.59.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2026 09:59:46 -0700 (PDT) X-Relaying-Domain: arista.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arista.com; s=Arista-A; t=1788195585; bh=Yz+SlEJxTrhVGNjozUlkHKCqwLCZLIFaEBLA1h4I/Gk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=nPhs2M/bzemz0ItWvdh/FZjFAeg/p+GeT6gfMTYhmDscg2KkWW+2S+fH552NT9Ixp WetIbfv0UcJWqrOWfo+jZ2h4I7h+LjTrpnprd2HVm7Kd28KG061OaS8g5P89J5GrSw /HXojO7zgfso5D6RU/Ig85w1uakjy0JXwxNVxVuP6/EtfL5x9A11p2PVTswbFYOPDg vPQoBXb35vTIpk7CVnf1dCV4Atvxv3qvSv1Qh+5EwdSudZmZZXpGuj+YCOiEZmLN/8 IuZs9+I4AXSaxUuZbK9MjCvJyQSY7E82BEzUKMMWdKqG1j4+S3NkHjO5gDkhxTYC3y fqKQrYUAppfqQ== Received: from vm-whiteberg-ubuntu.aristanetworks.com (dhcp-244-90-77.sjc.aristanetworks.com [10.244.90.77]) by smtp.aristanetworks.com (Postfix) with ESMTPS id 6E2C0C2E81; Mon, 31 Aug 2026 16:59:45 +0000 (UTC) X-SMTP-Authentication: Allow-List-permitted X-SMTP-Authentication: Allow-List-permitted From: Tate Whiteberg To: Andy Shevchenko , Jiri Slaby Cc: Tate Whiteberg , Greg Kroah-Hartman , Andy Shevchenko , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org Subject: [PATCH v3 2/2] serial: 8250_mid: wait for LSR tx empty before setting termios Date: Mon, 31 Aug 2026 16:59:08 +0000 Message-ID: <20260831165911.2029839-3-whiteberg@arista.com> In-Reply-To: <20260831165911.2029839-1-whiteberg@arista.com> References: <20260831165911.2029839-1-whiteberg@arista.com> Content-Transfer-Encoding: 8bit Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: If mid8250_set_termios is called while data is still in transmission, the corresponding register updates will corrupt the transmission. Fix this by locking the port and and waiting for the transmitter to empty before performing updates. It is necessary to wait for both UART_LSR_THRE and UART_LSR_TEMT to ensure the final character is sent. Fixes: f549e94effa1 ("serial: 8250_pci: add Intel Penwell ports") Signed-off-by: Tate Whiteberg --- Changes in v3: - Update Fixes tag - Apply formatting change from andriy.shevchenko@intel.com - Use scoped_guard() as suggested by jirislaby@kernel.org Changes in v2: - Separate changes to 8250.h and 8250_port.c into prerequisite patch, as recommended by andriy.shevchenko@intel.com - Apply feedback from andriy.shevchenko@intel.com to 8250_mid.c drivers/tty/serial/8250/8250_mid.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/drivers/tty/serial/8250/8250_mid.c b/drivers/tty/serial/8250/8250_mid.c index 82656645b8a6..9c5ef207bf8a 100644 --- a/drivers/tty/serial/8250/8250_mid.c +++ b/drivers/tty/serial/8250/8250_mid.c @@ -7,6 +7,7 @@ */ #include +#include #include #include #include @@ -209,6 +210,7 @@ static void mid8250_set_termios(struct uart_port *p, struct ktermios *termios, const struct ktermios *old) { unsigned int baud = tty_termios_baud_rate(termios); + struct uart_8250_port *up = up_to_u8250p(p); struct mid8250 *mid = p->private_data; unsigned short ps = 16; unsigned long fuart = baud * ps; @@ -231,11 +233,16 @@ static void mid8250_set_termios(struct uart_port *p, struct ktermios *termios, } rational_best_approximation(fuart, mid->board->freq, w, w, &mul, &div); - p->uartclk = fuart * 16 / ps; /* core uses ps = 16 always */ - writel(ps, p->membase + INTEL_MID_UART_PS); /* set PS */ - writel(mul, p->membase + INTEL_MID_UART_MUL); /* set MUL */ - writel(div, p->membase + INTEL_MID_UART_DIV); + scoped_guard(spinlock_irq, &p->lock) { + p->uartclk = fuart * 16 / ps; /* core uses ps = 16 always */ + + serial8250_wait_for_xmitr(up, UART_LSR_BOTH_EMPTY); + + writel(ps, p->membase + INTEL_MID_UART_PS); /* set PS */ + writel(mul, p->membase + INTEL_MID_UART_MUL); /* set MUL */ + writel(div, p->membase + INTEL_MID_UART_DIV); + } serial8250_do_set_termios(p, termios, old); } -- 2.43.0