From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 291CE3A875E for ; Mon, 31 Aug 2026 17:44:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788198275; cv=none; b=O22NjolfQSf1szjnv7s9n8wyWQnms22WOSCFAf/mxlJbSmddWouVQGuKD7uh7OcnQkGKCWT3bnsXqDp+gTvR813h2EyUoWvT0/utd4wyNgaAHJGxHxX0EACLTEyj2sv0S83ivcpdQERKQh7oqWjrGtEuyFk6ye+/pH1MjYBl3Bk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788198275; c=relaxed/simple; bh=ODSsZhaNXcNCS2/bN9jivq1/v46Qz9yhC1o4hFRi0zw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=QEbfe8aQMeDcbbjxOc1Ub8lKeSPewz2rlVtN1mHvVBWd7SgIX9xG5ZkLEW23o9jm9n+kaxvCSqZvOcrykFNyKBzhwzJDBXUrD0Pk3HFu2BITsKtQbW2NLvQ1S7HzaAJRVRqzTxwhD4Pc9R0fDqGN4FllDG1Gqh70yVboBwG5FoU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=A3HqLZjc; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="A3HqLZjc" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1788198273; x=1819734273; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ODSsZhaNXcNCS2/bN9jivq1/v46Qz9yhC1o4hFRi0zw=; b=A3HqLZjcsZVqp2wNoNVoJa+3hKyt7dzpeW/VxVN44DCiSnSS5dCOn5dH nzQhTQsZWqRaOYwudWxOj6yI5/VEarWH/kMtCMnOGkMuUE4BgT0nnEQpm iXc70fTQd85jqCKxa6YJyr29Rfdw6doCe0Q/Uo6lO4fWdKXR+XNK8m0YP xRNc1+cA3++B0OJ1zh4UHCtMwbGGNo2VfKOVUJOtD+66Z7ZXh6VThxT7n O9Net/ZJak/OQYoZvVgAQQwJtEotc4uHN3Ue+6Opb1ifbl5sHmh9BxUgM t87oFeWaWysc08DiJat+aW/LE7b/ioL60GMfWCI58Xxd+5bCNcoUYZY0n A==; X-CSE-ConnectionGUID: xxLdXzaoSoevplvt+WXp6g== X-CSE-MsgGUID: b7XsCPjoTuiF89+76Qji+g== X-IronPort-AV: E=McAfee;i="6800,10657,11892"; a="92479918" X-IronPort-AV: E=Sophos;i="6.25,254,1779174000"; d="scan'208";a="92479918" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Aug 2026 10:44:32 -0700 X-CSE-ConnectionGUID: McFFLRh1SLy6V6tOEPsfiA== X-CSE-MsgGUID: GLG0oqZZTZarzHnaF4Pehg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,254,1779174000"; d="scan'208";a="268906947" Received: from aherrold-mobl1.amr.corp.intel.com (HELO agluck-desk3.intel.com) ([10.124.220.17]) by orviesa007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Aug 2026 10:44:31 -0700 From: Tony Luck To: Fenghua Yu , Reinette Chatre , Maciej Wieczor-Retman , Peter Newman , James Morse , Babu Moger , Drew Fustini , Dave Martin , Chen Yu , David E Box , x86@kernel.org Cc: Christoph Hellwig , linux-kernel@vger.kernel.org, patches@lists.linux.dev, Tony Luck Subject: [PATCH v11 03/23] x86/resctrl: Enumerate monitor features in rdt_get_l3_mon_config() Date: Mon, 31 Aug 2026 10:44:01 -0700 Message-ID: <20260831174421.13921-4-tony.luck@intel.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260831174421.13921-1-tony.luck@intel.com> References: <20260831174421.13921-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The original implementation of Intel Cache QoS Monitoring (CQM) planned to integrate with the "perf" and "cgroup" subsystems. With that plan it made sense for parameters from CPUID to be stored in fields of the cpuinfo_x86 structure. But that plan was abandoned and the resctrl file system user interface replaced it. Enumerate the L3 monitoring features in rdt_get_l3_mon_config(). Signed-off-by: Tony Luck --- v11: New patch arch/x86/include/asm/resctrl.h | 9 ++++---- arch/x86/kernel/cpu/resctrl/monitor.c | 32 ++++++++++++++++++++++++--- 2 files changed, 33 insertions(+), 8 deletions(-) diff --git a/arch/x86/include/asm/resctrl.h b/arch/x86/include/asm/resctrl.h index 8f6edcdcfd87..9bfa9b14002b 100644 --- a/arch/x86/include/asm/resctrl.h +++ b/arch/x86/include/asm/resctrl.h @@ -44,6 +44,7 @@ DECLARE_PER_CPU(struct resctrl_pqr_state, pqr_state); extern bool rdt_alloc_capable; extern bool rdt_mon_capable; +extern unsigned int __ro_after_init rdt_l3_mon_scale; DECLARE_STATIC_KEY_FALSE(rdt_enable_key); DECLARE_STATIC_KEY_FALSE(rdt_alloc_enable_key); @@ -132,11 +133,9 @@ static inline void __resctrl_sched_in(struct task_struct *tsk) static inline unsigned int resctrl_arch_round_mon_val(unsigned int val) { - unsigned int scale = boot_cpu_data.x86_cache_occ_scale; - - /* h/w works in units of "boot_cpu_data.x86_cache_occ_scale" */ - val /= scale; - return val * scale; + /* Round down to nearest h/w monitoring unit */ + val /= rdt_l3_mon_scale; + return val * rdt_l3_mon_scale; } static inline void resctrl_arch_set_cpu_default_closid_rmid(int cpu, u32 closid, diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/resctrl/monitor.c index 3838e0a13d36..0c2aa20148a1 100644 --- a/arch/x86/kernel/cpu/resctrl/monitor.c +++ b/arch/x86/kernel/cpu/resctrl/monitor.c @@ -32,6 +32,11 @@ */ bool rdt_mon_capable; +/* + * Scale factor to convert L3 monitor events to bytes. + */ +unsigned int __ro_after_init rdt_l3_mon_scale; + #define CF(cf) ((unsigned long)(1048576 * (cf) + 0.5)) static int snc_nodes_per_l3_cache = 1; @@ -418,16 +423,37 @@ static __init int snc_get_config(void) int __init rdt_get_l3_mon_config(struct rdt_resource *r) { - unsigned int mbm_offset = boot_cpu_data.x86_cache_mbm_width_offset; struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); + unsigned int mbm_offset; unsigned int threshold; u32 eax, ebx, ecx, edx; + u32 num_rmid; + + /* QoS sub-leaf, EAX=0Fh, ECX=1 */ + cpuid_count(0xf, 1, &eax, &ebx, &ecx, &edx); + mbm_offset = eax & 0xff; + rdt_l3_mon_scale = ebx; + num_rmid = ecx + 1; + + if (!mbm_offset) { + switch (boot_cpu_data.x86_vendor) { + case X86_VENDOR_AMD: + mbm_offset = MBM_CNTR_WIDTH_OFFSET_AMD; + break; + case X86_VENDOR_HYGON: + mbm_offset = MBM_CNTR_WIDTH_OFFSET_HYGON; + break; + default: + /* Leave mbm_offset as 0 */ + break; + } + } snc_nodes_per_l3_cache = snc_get_config(); resctrl_rmid_realloc_limit = boot_cpu_data.x86_cache_size * 1024; - hw_res->mon_scale = boot_cpu_data.x86_cache_occ_scale / snc_nodes_per_l3_cache; - r->mon.num_rmid = (boot_cpu_data.x86_cache_max_rmid + 1) / snc_nodes_per_l3_cache; + hw_res->mon_scale = rdt_l3_mon_scale / snc_nodes_per_l3_cache; + r->mon.num_rmid = num_rmid / snc_nodes_per_l3_cache; hw_res->mbm_width = MBM_CNTR_WIDTH_BASE; if (mbm_offset > 0 && mbm_offset <= MBM_CNTR_WIDTH_OFFSET_MAX) -- 2.55.0