From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6F8763E49D6 for ; Mon, 31 Aug 2026 17:44:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788198277; cv=none; b=jdTpWqYGojQwBaON2CeOEwpfHw0IJ7a8lXgPhv5JKuG63Iv59Jv5U05p57/n92yFJaFeuoaWEl7MuBkAsSFeeQE2M0qTbi9+iYp24++LXqsRRONJ0N9F9jcJ3eTjaWc2vIwWhj+0fEcaCsAnV2tlFiNJotJb5xvoAA0BoRuswKs= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788198277; c=relaxed/simple; bh=MVoenKJyXcSb5Jiia+eBvMNI5XF3ytHBCSf+x/xE4CA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=pQjfkq2/4Yc3pECoiTeGLeRObrZrRXbSyh7UiUCMSQXHJw5EZGAVm3sLTdC4S6/du2/ONxQ0TVg1asoDZpHyGQvm2x96un/Rr78kEb1JWtZWCNWE21gGoHobrxCGvNdW3hgWKg/bDMo57/K7RBtfVbE5h3PE4Iu6cexEMCRUxl4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=E2ZyVGX+; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="E2ZyVGX+" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1788198275; x=1819734275; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=MVoenKJyXcSb5Jiia+eBvMNI5XF3ytHBCSf+x/xE4CA=; b=E2ZyVGX+KYmqEfP8xUGzKO2cSfmFHyCewND7LKd+DmP1pF+s8nqYH4WW Tb839+YRwS2DKRnSrD7xqp/c2Hihckb/jQFDLav8IRKHV8RjbnsLZn3mK hyus89GtDU1FZRkIS78KAHLLflTP6PoTgIxKrWhAlxN3FY7pq43S1zVsN zgikkCUHbn8QZBTYGkyDB2H0bKvzH7kApfCIbiMLnu0EYdZmkyn6WtLxe AVpyVFrC00XOp/6VSvcE9TpYVeyHK4KG0T1968zM9fvSptxm+tHIhH/cN xaCIa6xZCGx5UTcClEFR1Q+t7he1RtwKss0Ia0ePjLta4Lu/edgHZpi22 w==; X-CSE-ConnectionGUID: f4AWW/HgRyu2RhffMtb4GQ== X-CSE-MsgGUID: CqWtIIwBT0C5VSq9aqbr7g== X-IronPort-AV: E=McAfee;i="6800,10657,11892"; a="92479928" X-IronPort-AV: E=Sophos;i="6.25,254,1779174000"; d="scan'208";a="92479928" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Aug 2026 10:44:33 -0700 X-CSE-ConnectionGUID: Mz1Nnv/gSF2vVK6Ex5GBZg== X-CSE-MsgGUID: NKBuUQEFTsyQfij9q8uCxw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,254,1779174000"; d="scan'208";a="268906952" Received: from aherrold-mobl1.amr.corp.intel.com (HELO agluck-desk3.intel.com) ([10.124.220.17]) by orviesa007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Aug 2026 10:44:32 -0700 From: Tony Luck To: Fenghua Yu , Reinette Chatre , Maciej Wieczor-Retman , Peter Newman , James Morse , Babu Moger , Drew Fustini , Dave Martin , Chen Yu , David E Box , x86@kernel.org Cc: Christoph Hellwig , linux-kernel@vger.kernel.org, patches@lists.linux.dev, Tony Luck Subject: [PATCH v11 04/23] x86/resctrl: Apply Intel MBM quirk from rdt_get_l3_mon_config() Date: Mon, 31 Aug 2026 10:44:02 -0700 Message-ID: <20260831174421.13921-5-tony.luck@intel.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260831174421.13921-1-tony.luck@intel.com> References: <20260831174421.13921-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The Intel quirk to adjust Memory Bandwidth Monitoring (MBM) values on certain CPUs is applied early, before discovering if MBM is supported. Move the call to rdt_get_l3_mon_config(), but keep the decision on whether it is needed in __check_quirks_intel() with all the other model specific tests. Signed-off-by: Tony Luck --- v11: New patch arch/x86/kernel/cpu/resctrl/internal.h | 4 +-- arch/x86/kernel/cpu/resctrl/core.c | 2 +- arch/x86/kernel/cpu/resctrl/monitor.c | 35 +++++++++++++++----------- 3 files changed, 23 insertions(+), 18 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/resctrl/internal.h index e3cfa0c10e92..e46eb9a4c725 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -151,6 +151,8 @@ static inline struct rdt_hw_resource *resctrl_to_arch_res(struct rdt_resource *r extern struct rdt_hw_resource rdt_resources_all[]; +extern bool __initdata intel_rdt_mbm_need_quirk; + void arch_mon_domain_online(struct rdt_resource *r, struct rdt_l3_mon_domain *d); /* CPUID.(EAX=10H, ECX=ResID=1).EAX */ @@ -228,8 +230,6 @@ int rdt_get_l3_mon_config(struct rdt_resource *r); bool rdt_cpu_has(int flag); -void __init intel_rdt_mbm_apply_quirk(void); - void rdt_domain_reconfigure_cdp(struct rdt_resource *r); void resctrl_arch_mbm_cntr_assign_set_one(struct rdt_resource *r); diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c index fcbecf677914..0799dbfc7a72 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -1010,7 +1010,7 @@ static __init void __check_quirks_intel(void) set_rdt_options("!l3cat"); fallthrough; case INTEL_BROADWELL_X: - intel_rdt_mbm_apply_quirk(); + intel_rdt_mbm_need_quirk = true; break; } } diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/resctrl/monitor.c index 0c2aa20148a1..0bce199a5f7b 100644 --- a/arch/x86/kernel/cpu/resctrl/monitor.c +++ b/arch/x86/kernel/cpu/resctrl/monitor.c @@ -37,6 +37,8 @@ bool rdt_mon_capable; */ unsigned int __ro_after_init rdt_l3_mon_scale; +bool __initdata intel_rdt_mbm_need_quirk; + #define CF(cf) ((unsigned long)(1048576 * (cf) + 0.5)) static int snc_nodes_per_l3_cache = 1; @@ -51,7 +53,7 @@ static int snc_nodes_per_l3_cache = 1; * 1. The threshold 0 is changed to rmid count - 1 so don't do correction * for the case. * 2. MBM total and local correction table indexed by core counter which is - * equal to (x86_cache_max_rmid + 1) / 8 - 1 and is from 0 up to 27. + * equal to r->mon.num_rmid / 8 - 1 and is from 0 up to 27. * 3. The correction factor is normalized to 2^20 (1048576) so it's faster * to calculate corrected value by shifting: * corrected_value = (original_value * correction_factor) >> 20 @@ -421,6 +423,20 @@ static __init int snc_get_config(void) return ret; } +static void __init intel_rdt_mbm_apply_quirk(u32 num_rmid) +{ + int cf_index; + + cf_index = num_rmid / 8 - 1; + if (cf_index >= ARRAY_SIZE(mbm_cf_table)) { + pr_info("No MBM correction factor available\n"); + return; + } + + mbm_cf_rmidthreshold = mbm_cf_table[cf_index].rmidthreshold; + mbm_cf = mbm_cf_table[cf_index].cf; +} + int __init rdt_get_l3_mon_config(struct rdt_resource *r) { struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); @@ -500,25 +516,14 @@ int __init rdt_get_l3_mon_config(struct rdt_resource *r) hw_res->mbm_cntr_assign_enabled = true; } + if (intel_rdt_mbm_need_quirk) + intel_rdt_mbm_apply_quirk(r->mon.num_rmid); + r->mon_capable = true; return 0; } -void __init intel_rdt_mbm_apply_quirk(void) -{ - int cf_index; - - cf_index = (boot_cpu_data.x86_cache_max_rmid + 1) / 8 - 1; - if (cf_index >= ARRAY_SIZE(mbm_cf_table)) { - pr_info("No MBM correction factor available\n"); - return; - } - - mbm_cf_rmidthreshold = mbm_cf_table[cf_index].rmidthreshold; - mbm_cf = mbm_cf_table[cf_index].cf; -} - static void resctrl_abmc_set_one_amd(void *arg) { bool *enable = arg; -- 2.55.0