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Mon, 31 Aug 2026 17:38:18 -0700 (PDT) Received: from ryzen.lan ([2601:644:8000:7a86::e35]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-cc1f36aff95sm5000067a12.20.2026.08.31.17.38.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2026 17:38:17 -0700 (PDT) From: Rosen Penev To: linux-mmc@vger.kernel.org Cc: Adrian Hunter , Ulf Hansson , linux-kernel@vger.kernel.org (open list) Subject: [PATCH] mmc: sdhci-pxav3: disable clock inversion for SD HS cards Date: Mon, 31 Aug 2026 17:38:16 -0700 Message-ID: <20260901003816.48460-1-rosenp@gmail.com> X-Mailer: git-send-email 2.55.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The SDIO3 Configuration register branch of pxav3_set_uhs_signaling() only clears the clock-inversion and feedback-clock bits for MMC_TIMING_MMC_HS. As a result, MMC_TIMING_SD_HS (ordinary SD High Speed) falls through to the default case, which sets SDIO3_CONF_CLK_INV and leaves the feedback clock cleared. According to erratum FE-2946959, clock inversion is only needed for slow frequencies when the card hold-time requirement is high and is not required nor desirable for high-speed modes. SD High Speed runs at 50 MHz, so the same timing argument that applies to MMC High Speed holds. Treat MMC_TIMING_SD_HS the same as MMC_TIMING_MMC_HS and clear the clock-inversion and feedback-clock bits for both. Assisted-by: opencode:big-pickle Signed-off-by: Rosen Penev --- drivers/mmc/host/sdhci-pxav3.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c index db9dfa92cb57..9e6703e005e2 100644 --- a/drivers/mmc/host/sdhci-pxav3.c +++ b/drivers/mmc/host/sdhci-pxav3.c @@ -284,7 +284,8 @@ static void pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs) uhs == MMC_TIMING_UHS_DDR50) { reg_val &= ~SDIO3_CONF_CLK_INV; reg_val |= SDIO3_CONF_SD_FB_CLK; - } else if (uhs == MMC_TIMING_MMC_HS) { + } else if (uhs == MMC_TIMING_MMC_HS || + uhs == MMC_TIMING_SD_HS) { reg_val &= ~SDIO3_CONF_CLK_INV; reg_val &= ~SDIO3_CONF_SD_FB_CLK; } else { -- 2.55.0