From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8BE474279F9; Tue, 1 Sep 2026 07:26:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.75.126.72 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788247563; cv=none; b=RZWa+kl29vcKrrdzfs0t+VGGh6dEk6nEDK+/yCdqjs7b7h3p7TgvsdY6i+3Gxa2LPLBfDrvvpEbbPnrmfkQ+0ivF2xsRFFiY61LUJZXEH20Er3GQ75MQ58BmWJ2onT6SYnvpCJ/2JpoGWOzaTFUdHeUq8kAejPFFzztATwczB7Y= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788247563; c=relaxed/simple; bh=7sijnYjFURDdPMtz00iULltouwj5Fko94kgcRRLSXNw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=BRiVB2ivnOd5fZkSBcEkBmpNHqcPm0qD9tPwRCgUbt3VP4LbcTMUIomlDrKLNOxbsoeukDzcjMwmaLkMwatgJa67WUo37zxqCvFSGMOULGdm1zG1H35ZdJzEMMqoJM7kXpHp5VIi5ERGdcNzsGnnRZUS2HyptbBTiL3NZA9cGvQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realtek.com; spf=pass smtp.mailfrom=realtek.com; dkim=pass (2048-bit key) header.d=realtek.com header.i=@realtek.com header.b=MkhvzC/G; arc=none smtp.client-ip=211.75.126.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realtek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=realtek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=realtek.com header.i=@realtek.com header.b="MkhvzC/G" X-SpamFilter-By: ArmorX SpamTrap 5.80 with qID 6817P13O01484621, This message is accepted by code: ctloc85258 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=realtek.com; s=dkim; t=1788247501; bh=DPWcFo0yU6+j3gkQUbftg0xAU3W/3+jUteLM8DNIF7E=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Transfer-Encoding:Content-Type; b=MkhvzC/GYOj7uNr4+ELQ0SaeYrhQPtcCBS26WY0qRNblFRk7WYpMSJSW+GuZmp3nX 2JEIus907F3E0Dtk8cI524kttYJtCJoEizrvUygOcsns4ngp7YenX7mLTtnFxcMoae 1krA0JVWfjdrhhhXDIUwuZLHs1S7zoXt8kATIWasN+1bAn6W2W/XYkR6WC26het91j WHbr10QRVWW9MmVQnM89v20TOams7UdOfFfqqx62NCb/vrV7iGfrDNOnA8oIY8Fu0J AxT+bGut3xECAHeqGI72vA0kXwLVNMJVE3P9dqYyWTZ++sEElMQ1rL2M7NbHsI625l pC0MU5My7/BmA== Received: from mail.realtek.com (rtkexhmbs02.realtek.com.tw[172.21.6.41]) by rtits2.realtek.com.tw (8.15.2/3.29/5.94) with ESMTPS id 6817P13O01484621 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 1 Sep 2026 15:25:01 +0800 Received: from RTKEXHMBS04.realtek.com.tw (10.21.1.54) by RTKEXHMBS02.realtek.com.tw (172.21.6.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.43; Tue, 1 Sep 2026 15:24:59 +0800 Received: from cn1dhc-k02 (172.21.252.101) by RTKEXHMBS04.realtek.com.tw (10.21.1.54) with Microsoft SMTP Server id 15.2.2562.43 via Frontend Transport; Tue, 1 Sep 2026 15:24:57 +0800 From: Yu-Chun Lin To: , , , , , , , , , CC: , , , , , , , , , Brian Masney Subject: [PATCH v14 07/11] clk: realtek: Add support for mux clock Date: Tue, 1 Sep 2026 15:24:42 +0800 Message-ID: <20260901072446.2563145-8-eleanor.lin@realtek.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260901072446.2563145-1-eleanor.lin@realtek.com> References: <20260901072446.2563145-1-eleanor.lin@realtek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain From: Cheng-Yu Lee Add a simple regmap-based clk_ops implementation for Realtek mux clocks. The implementation supports parent selection and rate determination through regmap-backed register access. Signed-off-by: Cheng-Yu Lee Co-developed-by: Yu-Chun Lin Reviewed-by: Brian Masney Signed-off-by: Yu-Chun Lin --- Changes in v14: - Move Reviewed-by tag to the correct position. --- drivers/clk/realtek/Makefile | 1 + drivers/clk/realtek/clk-regmap-mux.c | 41 ++++++++++++++++++++++++++ drivers/clk/realtek/clk-regmap-mux.h | 43 ++++++++++++++++++++++++++++ 3 files changed, 85 insertions(+) create mode 100644 drivers/clk/realtek/clk-regmap-mux.c create mode 100644 drivers/clk/realtek/clk-regmap-mux.h diff --git a/drivers/clk/realtek/Makefile b/drivers/clk/realtek/Makefile index 840aff067b61..217ccaf5644a 100644 --- a/drivers/clk/realtek/Makefile +++ b/drivers/clk/realtek/Makefile @@ -4,4 +4,5 @@ obj-$(CONFIG_RTK_CLK_COMMON) += clk-rtk.o clk-rtk-y += clk-rtk-common.o clk-rtk-y += clk-pll.o clk-rtk-y += clk-regmap-gate.o +clk-rtk-y += clk-regmap-mux.o clk-rtk-y += freq_table.o diff --git a/drivers/clk/realtek/clk-regmap-mux.c b/drivers/clk/realtek/clk-regmap-mux.c new file mode 100644 index 000000000000..1069c95595aa --- /dev/null +++ b/drivers/clk/realtek/clk-regmap-mux.c @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2017-2026 Realtek Semiconductor Corporation + * Author: Cheng-Yu Lee + */ + +#include +#include +#include +#include "clk-regmap-mux.h" + +static u8 rtk_clk_regmap_mux_get_parent(struct clk_hw *hw) +{ + struct rtk_clk_regmap_mux *clkm = to_rtk_clk_regmap_mux(hw); + unsigned int num_parents = clk_hw_get_num_parents(hw); + u32 val; + int ret; + + ret = regmap_read(clkm->clkr.regmap, clkm->mux_ofs, &val); + if (ret) + return 0xff; + + val = (val >> clkm->shift) & clkm->mask; + + return val >= num_parents ? 0xff : val; +} + +static int rtk_clk_regmap_mux_set_parent(struct clk_hw *hw, u8 index) +{ + struct rtk_clk_regmap_mux *clkm = to_rtk_clk_regmap_mux(hw); + + return regmap_update_bits(clkm->clkr.regmap, clkm->mux_ofs, + clkm->mask << clkm->shift, (u32)index << clkm->shift); +} + +const struct clk_ops rtk_clk_regmap_mux_ops = { + .set_parent = rtk_clk_regmap_mux_set_parent, + .get_parent = rtk_clk_regmap_mux_get_parent, + .determine_rate = __clk_mux_determine_rate, +}; +EXPORT_SYMBOL_NS_GPL(rtk_clk_regmap_mux_ops, "CLK_REALTEK"); diff --git a/drivers/clk/realtek/clk-regmap-mux.h b/drivers/clk/realtek/clk-regmap-mux.h new file mode 100644 index 000000000000..ad524bb86a19 --- /dev/null +++ b/drivers/clk/realtek/clk-regmap-mux.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2017-2026 Realtek Semiconductor Corporation + * Author: Cheng-Yu Lee + */ + +#ifndef __CLK_REALTEK_CLK_REGMAP_MUX_H +#define __CLK_REALTEK_CLK_REGMAP_MUX_H + +#include "clk-rtk-common.h" + +struct rtk_clk_regmap_mux { + struct rtk_clk_regmap clkr; + unsigned int mux_ofs; + unsigned int mask; + unsigned int shift; +}; + +#define __rtk_clk_regmap_mux_hw(_p) __rtk_clk_regmap_hw(&(_p)->clkr) + +#define __RTK_CLK_REGMAP_MUX(_name, _parents, _ops, _flags, _ofs, _sft, _mask) \ + struct rtk_clk_regmap_mux _name = { \ + .clkr.hw.init = \ + CLK_HW_INIT_PARENTS(#_name, _parents, _ops, _flags), \ + .mux_ofs = _ofs, \ + .shift = _sft, \ + .mask = _mask, \ + } + +#define RTK_CLK_REGMAP_MUX(_name, _parents, _flags, _ofs, _sft, _mask) \ + __RTK_CLK_REGMAP_MUX(_name, _parents, &rtk_clk_regmap_mux_ops, _flags, _ofs, \ + _sft, _mask) + +static inline struct rtk_clk_regmap_mux *to_rtk_clk_regmap_mux(struct clk_hw *hw) +{ + struct rtk_clk_regmap *clkr = to_rtk_clk_regmap(hw); + + return container_of(clkr, struct rtk_clk_regmap_mux, clkr); +} + +extern const struct clk_ops rtk_clk_regmap_mux_ops; + +#endif /* __CLK_REALTEK_CLK_REGMAP_MUX_H */ -- 2.43.0