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[79.26.252.140]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-48442d3d2eesm4644130f8f.15.2026.09.01.05.39.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Sep 2026 05:39:45 -0700 (PDT) From: Christian Marangi To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Christian Marangi , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 2/3] dt-bindings: phy: airoha: Document support for AN7583 Gen2 PCIe PHY Date: Tue, 1 Sep 2026 14:39:32 +0200 Message-ID: <20260901123933.15388-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260901123933.15388-1-ansuelsmth@gmail.com> References: <20260901123933.15388-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Document support for AN7583 Gen2 PCIe PHY used to make the Gen2 PCIe port work. Add the required register to configure the PCIe PHY and provide an example for it. Similar to the USB 3.0 PHY, a dedicated phys property is required to configure the serdes for PCIe or Ethernet usage. Signed-off-by: Christian Marangi --- .../phy/airoha,an7583-pcie-gen2-phy.yaml | 63 +++++++++++++++++++ 1 file changed, 63 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/airoha,an7583-pcie-gen2-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/airoha,an7583-pcie-gen2-phy.yaml b/Documentation/devicetree/bindings/phy/airoha,an7583-pcie-gen2-phy.yaml new file mode 100644 index 000000000000..424da3c5ad01 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/airoha,an7583-pcie-gen2-phy.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/airoha,an7583-pcie-gen2-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Airoha AN7583 SoC PCIe Gen2 PHY + +maintainers: + - Christian Marangi + +description: > + The Airoha AN7583 SoC PCIe Gen2 PHY describes the PCIe PHY for the + Gen2 PCIe controller. + + This PCIe PHY makes use of a dedicated USB PHY for PCIe usage and + can also be used for Ethernet usage for SGMII or HSGMII mode. + +properties: + compatible: + const: airoha,an7583-pcie-gen2-phy + + reg: + items: + - description: ana register + - description: pma register + - description: dig register + + reg-names: + items: + - const: ana + - const: pma + - const: dig + + phys: + items: + - description: phandle to Serdes PHY + + '#phy-cells': + const: 0 + +required: + - compatible + - reg + - reg-names + - phys + - '#phy-cells' + +additionalProperties: false + +examples: + - | + phy@1fa5f000 { + compatible = "airoha,an7583-pcie-gen2-phy"; + reg = <0x1fa5f000 0x100>, + <0x1fa5e000 0x400>, + <0x1fa5a000 0x900>; + reg-names = "ana", "pma", "dig"; + + phys = <&serdes_phy>; + + #phy-cells = <0>; + }; -- 2.53.0