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[86.49.251.7]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c255f1b2901sm582378466b.33.2026.09.01.06.38.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Sep 2026 06:38:40 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com Subject: Re: [PATCH v5 11/17] irqchip/riscv-imsic: Add S-mode MSI address list Date: Tue, 1 Sep 2026 15:38:34 +0200 Message-ID: <20260901133835.345001-1-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260831145943.313726-12-andrew.jones@oss.qualcomm.com> References: <20260831145943.313726-1-andrew.jones@oss.qualcomm.com> <20260831145943.313726-12-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=beZbluPB c=1 sm=1 tr=0 ts=6a96d74b cx=c_pps a=wURt19dY5n+H4uQbQt9s7g==:117 a=on9AXyaqQ0RhfYpiXjjEXA==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=rNTwnVtw_qv2rMTDxuYA:9 a=-UhsvdU3ccFDOXFxFb4l:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTAxMDEyMiBTYWx0ZWRfX//qeXO78i15H qjjtNUQyLviU1nt3ET26+tAcPYz+KbolDftqTwiq4p7GVU5FEl6nQKGPICuxXww3ng5IebpjpAH nRANUQocBsqOEkcsthCTE0L7tRofHET7lAqua2QWPjSZErGV+p+OG6phK0x60wQ/9eJn6GKxinz pY5vXxy4SJz+5iwx1qb/wQF6Zv0op8vuYevEKUvycH2xFmyNsIrW6ObXsqNr4LEiaQ1Kx12aH7/ O3wIet0OtzV/VJ452A1tjiwFjrEml0uh6Tq2Z8ZW2s6LqN9uchf/DZkipjTY+0yFt4nGPNmXaz4 79Ve8kbX2F+tNFcNvboDZdu6+Bbl+1gBl5F2nvBep/UNVXI+1grcAhV2YdbWXfMjdQMgP0te0yK 5/GByAZqnpz4Scrcs9zre5DjA7gARQ4yjzd+F79A0m5wa2965PQLRzS0uoPu8EOEdvme3a0akc4 lbmgwXi4IUKAEeui4Yg== X-Proofpoint-GUID: hBH33MulRO-8asenVKTfxxA2oeE2CSqQ X-Proofpoint-ORIG-GUID: hBH33MulRO-8asenVKTfxxA2oeE2CSqQ X-Proofpoint-Spam-Info: AW1haW4tMjYwOTAxMDEyMiBTYWx0ZWRfXz4bclyev9trA KZ1EJNWysjMxByiv/EDZBXNhW9KiRTWYxZgN0L2BYUXeb7mFTSaWohXaVGonFJSKbyC9uQMC4bc /S3TVDlZqZuPxvYAGW002VfFuZ468yM= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-01_03,2026-09-01_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 lowpriorityscore=0 bulkscore=0 clxscore=1015 impostorscore=0 priorityscore=1501 malwarescore=0 spamscore=0 adultscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609010122 A Sashiko review raised the following questions: > + if (!local->msi_va) { > + kfree(smode_msi_pa); > + return -ENODEV; > > Does this strict requirement introduce a regression on systems with partial > IMSIC coverage? > > By returning -ENODEV here if any possible CPU lacks an IMSIC mapping, the > error bubbles up to imsic_setup_state() and fatally tears down the entire > driver. Previously, imsic_setup_state() allowed partial coverage as long as > at least one CPU handler was found. Partial IMSIC coverage is not functionally supported. The IPI and MSI paths can select any online CPU and unconditionally use that CPU's local->msi_va or local->msi_pa, so every possible CPU must have an initialized IMSIC page. Returning -ENODEV during setup therefore validates this invariant earlier. > > + smode_msi_pa[cpu] = local->msi_pa; > > Could this assignment cause an out-of-bounds write on systems where the CPU > mask is sparse? > > The smode_msi_pa array is allocated using num_possible_cpus() (the count of > possible CPUs) but is indexed here by the logical CPU ID. If the CPU mask has > gaps (for example, if logical CPUs 0 and 2 are present), num_possible_cpus() > would evaluate to 2, but this loop would attempt to write to index 2, > overflowing the bounds of the array. Would allocating based on nr_cpu_ids > prevent this issue? For RISC-V, num_possible_cpus() == nr_cpu_ids because RISC-V assigns logical CPU IDs sequentially during both DT and ACPI discovery and populates the possible mask from those contiguous mappings. Thanks, drew