From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0E6BE30F7FA for ; Tue, 1 Sep 2026 13:08:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788268092; cv=none; b=AwTMafZ9erHaUoBLfmYz37qABCEko8XKxj5fZT9yrj+FXTvbaEybMarF2iYibQHmgS5xww6LIzoxq1grJigdM2dRkAVcRhq5mAAJIi2Uta8noEKDgIyoCQ7swTEC7Ca/0/rIjjqsZ+wECdzpIywKRc3+kUsuQUG7e19fFDIZHdg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788268092; c=relaxed/simple; bh=qH64igqWmhbPPqereCNZa1DEz1woVgjOvI/xPj3Lx8s=; h=Date:From:To:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=FnifBRTyZFT65LkEihjKh8ZDZvigzXpaCAIyL30lX+WZnh816Mrk6pv6IznfzLCD78sHyqk8YnPvrT/m130h2wYNYIliKVuE8tw66boYuFSpBT5XoV7l4NUV/l4x3Up86FTaNpvHN68ndGLe4Kw8sKOLf5DlW6zjsZBDKko7Z/8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=FCqLq1wj; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="FCqLq1wj" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1788268088; bh=qH64igqWmhbPPqereCNZa1DEz1woVgjOvI/xPj3Lx8s=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=FCqLq1wjHQYD1btvljkUdwtODyAwZQyQdQKalOf1PZZYUbWb2ZsV8n0JmlL3rEHcj CVdcBOIG6cncmviEIPytcxC23KlY3RflHwhcQymkObO0hGp7ot31/J9gKkvk2dZZD+ WGqPRmi3HbFdZO7J7ZB9b88s0dNq0mHKmvG+0aLYuMsgIow6qL62YrnxTxRnsZCRhh YxVtRPypWSqWTZErVScEGuQIBphq+41tTGIQe9binjZnnUTqCjslE5ocdWxG6nG8lL ZexKq0pgtq0FTxOim8UXEUuNwsnRZy8gPhRYPP/UV93ua+6Tp0Jgaurz2mmL1ahXeN QJ4lMRGgzIIiQ== Received: from fedora-21.home (unknown [100.64.0.11]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange secp256r1 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: bbrezillon) by bali.collaboradmins.com (Postfix) with ESMTPSA id 3844617E006A; Tue, 01 Sep 2026 15:08:08 +0200 (CEST) Date: Tue, 1 Sep 2026 15:08:04 +0200 From: Boris Brezillon To: =?UTF-8?B?QWRyacOhbg==?= Larumbe Cc: Rob Herring , Steven Price , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Faith Ekstrand , "Marty E. Plummer" , Tomeu Vizoso , Eric Anholt , Alyssa Rosenzweig , Robin Murphy , Philipp Zabel , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Collabora Kernel Team , Neil Armstrong Subject: Re: [PATCH v7 08/17] drm/panfrost: Split subsystem init/reset from interrupt enablement Message-ID: <20260901150804.75ce2f47@fedora-21.home> In-Reply-To: <20260828-claude-fixes-v7-8-72a13b2c125d@collabora.com> References: <20260828-claude-fixes-v7-0-72a13b2c125d@collabora.com> <20260828-claude-fixes-v7-8-72a13b2c125d@collabora.com> Organization: Collabora X-Mailer: Claws Mail 4.4.0 (GTK 3.24.52; x86_64-redhat-linux-gnu) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable On Fri, 28 Aug 2026 21:56:48 +0100 Adri=C3=A1n Larumbe wrote: > Because MMU interrupts are only enabled when the device is reset, it > happened that after DRM device registration, the very first job targeting > the tiler heap BO would always time out. The reason is the reset sequence > is only part of PM runtime resume, which is not called explicitly at driv= er > probe time, and an actual reset work item manually triggered after a HW > error. >=20 > I have attempted a somewhat drastic solution, which is completely > decoupling GPU/MMU/JM subsystem initialisation and reset from interrupt > enablement, so that we can handle IRQ toggling a bit more flexibly. >=20 > To this end: > - Ensure every subsystem with its own IRQ has an 'enable interrupts' > method, and that it doesn't enable them anywhere else. > - Force IRQ masking at MMU reset time. Up until, now, panfrost_mmu_reset() > was clearing the MMU IRQ suspension bit, but at no point that is set duri= ng > the reset sequence. >=20 > Then manually enable all interrupts when the device is fully initialised = at > probe time, right before DRM device registration, or after the reset > sequence is complete. Also disable all interrupts at device remove time, > so that their IRQs can be sync'ed right before tearing the device down. >=20 > Fixes: 635430797d3f ("drm/panfrost: Rework runtime PM initialization") > Fixes: 876b15d2c88d ("drm/panfrost: Fix module unload") > Signed-off-by: Adri=C3=A1n Larumbe > --- > drivers/gpu/drm/panfrost/panfrost_device.c | 40 ++++++++++++++++++++++--= ------ > drivers/gpu/drm/panfrost/panfrost_device.h | 3 ++- > drivers/gpu/drm/panfrost/panfrost_gpu.c | 19 ++++++++------ > drivers/gpu/drm/panfrost/panfrost_gpu.h | 2 ++ > drivers/gpu/drm/panfrost/panfrost_job.c | 7 +++--- > drivers/gpu/drm/panfrost/panfrost_mmu.c | 9 +++++-- > drivers/gpu/drm/panfrost/panfrost_mmu.h | 2 ++ > 7 files changed, 56 insertions(+), 26 deletions(-) >=20 > diff --git a/drivers/gpu/drm/panfrost/panfrost_device.c b/drivers/gpu/drm= /panfrost/panfrost_device.c > index 9e02fb5f73c8..99f7da2180f9 100644 > --- a/drivers/gpu/drm/panfrost/panfrost_device.c > +++ b/drivers/gpu/drm/panfrost/panfrost_device.c > @@ -226,6 +226,27 @@ static int panfrost_pm_domain_init(struct panfrost_d= evice *pfdev) > return err; > } > =20 > +void panfrost_device_enable_int(struct panfrost_device *pfdev) > +{ > + panfrost_gpu_enable_interrupts(pfdev); > + panfrost_mmu_enable_interrupts(pfdev); > + panfrost_jm_enable_interrupts(pfdev); > +} > + > +static void panfrost_device_enable_hw(struct panfrost_device *pfdev) > +{ > + panfrost_device_enable_int(pfdev); > + panfrost_devfreq_resume(pfdev); > +} > + > +static void panfrost_device_disable_hw(struct panfrost_device *pfdev) > +{ > + panfrost_devfreq_suspend(pfdev); > + panfrost_jm_suspend_irq(pfdev); > + panfrost_mmu_suspend_irq(pfdev); > + panfrost_gpu_suspend_irq(pfdev); Hm, I think I'd prefer if those suspend/resume_irq() were hidden in some subcomponent panfrost__suspend,resume() helpers. And then we just have to resume/suspend component in the right order instead of treating IRQs as a standalone object (enabling/disabling only makes sense if the subcomponent handling those interrupts is resumed/suspended).