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[87.9.102.148]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49cdd73f7a4sm139618475e9.12.2026.09.02.03.15.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Sep 2026 03:15:36 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Abel Vesa , Brian Masney , Fabio Estevam , Frank Li , Jerome Brunet , Peng Fan , Pengutronix Kernel Team , Sascha Hauer , Stephen Boyd , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v12 3/3] clk: imx: pll14xx: support spread spectrum clock generation Date: Wed, 2 Sep 2026 12:07:35 +0200 Message-ID: <20260902101515.167819-4-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260902101515.167819-1-dario.binacchi@amarulasolutions.com> References: <20260902101515.167819-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add support for spread spectrum clock (SSC) generation to the pll14xx driver. Tested on the video PLL of i.MX8MN and i.MX8MP based boards. Signed-off-by: Dario Binacchi --- Changes in v12: - Apply the SSC settings also from the set_spread_spectrum() callback to handle the case the clock framework skips set_rate() if the requested rate is unchanged. Changes in v11: - Drop the dt-bindings/clock/clock.h include and use the enum clk_ssc_method values from clk-provider.h, as clk-scmi-oem.c does. - Disable SSC and clear the modulation fields in SSCG_CTRL when no spread method is configured, so that a setup left enabled by the bootloader is not kept active. - Skip the SSC setup instead of dividing by zero when modfreq_hz is zero or mfr truncates to zero. - Reject mfr and mrr values that do not fit the MFREQ_CTL and MRAT_CTL register fields instead of letting FIELD_PREP silently truncate them. This also prevents the 10000 * mfr multiplication from overflowing. - Compute the mfr divisor in 64-bit arithmetic, as the 32-bit product could wrap with out of range modfreq_hz values. Changes in v10: - Drop 'Reviewed-by' tag of Peng Fan. - Adapt the driver to the new infrastructure. Implement the set_spread_spectrum() and get the modulation parameters from struct clk_spread_spectrum. Changes in v9: - Add 'Reviewed-by' tag of Peng Fan. drivers/clk/imx/clk-pll14xx.c | 99 +++++++++++++++++++++++++++++++++++ 1 file changed, 99 insertions(+) diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c index b6f1cc9f5700..5b187101c558 100644 --- a/drivers/clk/imx/clk-pll14xx.c +++ b/drivers/clk/imx/clk-pll14xx.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -22,6 +23,8 @@ #define GNRL_CTL 0x0 #define DIV_CTL0 0x4 #define DIV_CTL1 0x8 +#define SSCG_CTRL 0xc + #define LOCK_STATUS BIT(31) #define LOCK_SEL_MASK BIT(29) #define CLKE_MASK BIT(11) @@ -33,6 +36,13 @@ #define KDIV_MASK GENMASK(15, 0) #define KDIV_MIN SHRT_MIN #define KDIV_MAX SHRT_MAX +#define SSCG_ENABLE BIT(31) +#define MFREQ_CTL_MASK GENMASK(19, 12) +#define MRAT_CTL_MASK GENMASK(9, 4) +#define SEL_PF_DOWN_SPREAD 0 +#define SEL_PF_UP_SPREAD 1 +#define SEL_PF_CENTER_SPREAD 2 +#define SEL_PF_MASK GENMASK(1, 0) #define LOCK_TIMEOUT_US 10000 @@ -44,6 +54,7 @@ struct clk_pll14xx { int rate_count; s16 delta_k; spinlock_t lock; + struct clk_spread_spectrum ss_conf; }; #define to_clk_pll14xx(_hw) container_of(_hw, struct clk_pll14xx, hw) @@ -366,6 +377,58 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate, return 0; } +static void __clk_pll1443x_set_spread_spectrum(struct clk_hw *hw, + unsigned long parent_rate, + unsigned int pdiv, + unsigned int mdiv) +{ + struct clk_pll14xx *pll = to_clk_pll14xx(hw); + struct clk_spread_spectrum *conf = &pll->ss_conf; + u32 sscg_ctrl, mfr, mrr, sel_pf; + + sscg_ctrl = readl_relaxed(pll->base + SSCG_CTRL); + sscg_ctrl &= ~(SSCG_ENABLE | MFREQ_CTL_MASK | MRAT_CTL_MASK | SEL_PF_MASK); + + switch (conf->method) { + case CLK_SPREAD_CENTER: + sel_pf = SEL_PF_CENTER_SPREAD; + break; + case CLK_SPREAD_UP: + sel_pf = SEL_PF_UP_SPREAD; + break; + case CLK_SPREAD_DOWN: + sel_pf = SEL_PF_DOWN_SPREAD; + break; + default: + /* No spread: disable modulation and clear any stale state */ + goto out; + } + + if (!conf->modfreq_hz || !parent_rate || !pdiv) + goto out; + + mfr = div64_u64(parent_rate, (u64)conf->modfreq_hz * pdiv * BIT(5)); + if (!mfr || mfr > FIELD_MAX(MFREQ_CTL_MASK)) { + pr_warn("%s: SSC disabled, modulation frequency (%u Hz) out of range\n", + clk_hw_get_name(hw), conf->modfreq_hz); + goto out; + } + + mrr = (conf->spread_bp * mdiv * BIT(6)) / (10000 * mfr); + if (!mrr || mrr > FIELD_MAX(MRAT_CTL_MASK)) { + pr_warn("%s: SSC disabled, spread (%u permyriad) out of range\n", + clk_hw_get_name(hw), conf->spread_bp); + goto out; + } + + sscg_ctrl |= SSCG_ENABLE | FIELD_PREP(MFREQ_CTL_MASK, mfr) | + FIELD_PREP(MRAT_CTL_MASK, mrr) | + FIELD_PREP(SEL_PF_MASK, sel_pf); + +out: + writel_relaxed(sscg_ctrl, pll->base + SSCG_CTRL); +} + static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, unsigned long prate) { @@ -390,6 +453,9 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, writel_relaxed(FIELD_PREP(KDIV_MASK, rate.kdiv), pll->base + DIV_CTL1); + __clk_pll1443x_set_spread_spectrum(hw, prate, rate.pdiv, + rate.mdiv); + spin_unlock_irqrestore(&pll->lock, flags); return 0; @@ -411,6 +477,8 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, writel_relaxed(FIELD_PREP(KDIV_MASK, rate.kdiv), pll->base + DIV_CTL1); + __clk_pll1443x_set_spread_spectrum(hw, prate, rate.pdiv, rate.mdiv); + spin_unlock_irqrestore(&pll->lock, flags); /* @@ -437,6 +505,36 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, return 0; } +static int clk_pll1443x_set_spread_spectrum(struct clk_hw *hw, + const struct clk_spread_spectrum *ss_conf) +{ + struct clk_pll14xx *pll = to_clk_pll14xx(hw); + struct clk_hw *parent = clk_hw_get_parent(hw); + unsigned long parent_rate = parent ? clk_hw_get_rate(parent) : 0; + unsigned long flags; + u32 div_ctl0; + + spin_lock_irqsave(&pll->lock, flags); + + pll->ss_conf = *ss_conf; + + /* + * Apply the configuration to the hardware right away, using the + * current PLL dividers: the clock framework does not call set_rate() + * if the requested rate is unchanged, so relying on it would leave + * the SSC settings unapplied when the PLL is already at the target + * rate (e.g. configured by the bootloader). + */ + div_ctl0 = readl_relaxed(pll->base + DIV_CTL0); + __clk_pll1443x_set_spread_spectrum(hw, parent_rate, + FIELD_GET(PDIV_MASK, div_ctl0), + FIELD_GET(MDIV_MASK, div_ctl0)); + + spin_unlock_irqrestore(&pll->lock, flags); + + return 0; +} + static int clk_pll14xx_prepare(struct clk_hw *hw) { struct clk_pll14xx *pll = to_clk_pll14xx(hw); @@ -509,6 +607,7 @@ static const struct clk_ops clk_pll1443x_ops = { .recalc_rate = clk_pll14xx_recalc_rate, .determine_rate = clk_pll1443x_determine_rate, .set_rate = clk_pll1443x_set_rate, + .set_spread_spectrum = clk_pll1443x_set_spread_spectrum, }; struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *dev, const char *name, -- 2.43.0