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[82.69.66.36]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49cee3b0af8sm10644075e9.0.2026.09.02.11.19.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Sep 2026 11:19:57 -0700 (PDT) Date: Wed, 2 Sep 2026 19:19:56 +0100 From: David Laight To: Eric Biggers Cc: Christoph Hellwig , Andrew Morton , linux-raid@vger.kernel.org, linux-kernel@vger.kernel.org, x86@kernel.org, stable@vger.kernel.org Subject: Re: [PATCH RESEND] xor: add missing vzeroupper to AVX code Message-ID: <20260902191956.0834eaa3@pumpkin> In-Reply-To: <20260902162359.GA2497@quark> References: <20260831212248.213805-1-ebiggers@kernel.org> <20260902133706.GA21538@lst.de> <20260902162359.GA2497@quark> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; arm-unknown-linux-gnueabihf) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Wed, 2 Sep 2026 09:23:59 -0700 Eric Biggers wrote: > On Wed, Sep 02, 2026 at 03:37:06PM +0200, Christoph Hellwig wrote: > > On Mon, Aug 31, 2026 at 02:22:48PM -0700, Eric Biggers wrote: > > > Since the AVX optimized XOR code uses YMM registers, execute vzeroupper > > > before returning from it. This is needed to avoid degrading the > > > performance of any later SSE code that may happen to be executed. > > > > > > Fixes: ea4d26ae24e5 ("raid5: add AVX optimized RAID5 checksumming") > > > Cc: stable@vger.kernel.org > > > Signed-off-by: Eric Biggers > > > --- > > > > > > This didn't get taken through the x86 tree. Andrew, it seems you're > > > taking patches to lib/raid/. Can you apply this one? > > > > Can we do kernel_avx_{begin,end} instead of having to open code > > and document this everywhere, please? > > Again, there are cases in the kernel where both AVX and SSE are used > within a single kernel-mode FPU section, or where a CPU feature check > occurs within the section and one or the other is used. So that > abstraction will not work as-is, and it would be different from all > userspace code as well. If you'd like to try to refactor everything you > can try to do so, but let's not block fixing these bugs first. > > Also, AVX != "vzeroupper is needed". The relevant thing is the width of > the registers used. There is 128-bit AVX code. It also depends on the instruction encoding used for 128-bit AVX code. If the VEX encoding is used the high bits of the ymm registers get cleared (rather than preserved) and you get different delays. Flipping to/from VEX encoded 128bit instructions adds delays on some cpu. Yes, it is all a mess.... David > > - Eric >