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This is based on the size of the "Count" field of the MCG_CAP registers. The "Count" field is 8 bits and holds the number of MCA banks per CPU thread. So the value range is 0-255. Change the MAX_NR_BANKS value to match the architectural definition. Drop the clamps in __mcheck_cpu_cap_init() and cmci_supported(). MCG_CAP[Count] can no longer exceed MAX_NR_BANKS, so neither is reachable. MAX_NR_BANKS sizes a number of arrays and bitmaps. Growing it by 191 banks costs the following, measured with size -A on the MCA objects built from x86_64 defconfig. Global bitmaps: - core.c / mce_banks_ce_disabled - Total: 191 new bits = 24 new bytes Per-CPU bitmaps: - core.c / mce_poll_banks - intel.c / mce_banks_owned - amd.c / bank_map - amd.c / mce_amd_data: thr_intr_banks and dfr_intr_banks - Total: 191 new bits * 5 bitmaps = 120 new bytes Global structs: - core.c / struct mce_bank_dev mce_bank_devs[]: 56 bytes per bank - intel.c / u16 cmci_threshold[]: 2 bytes per bank - Total: 191 new banks * 58 bytes = 11078 new bytes Per-CPU structs: - core.c / struct mce_bank mce_banks_array[]: 16 bytes per bank - amd.c / struct smca_bank smca_banks[]: 24 bytes per bank - threshold.c / struct mca_storm_desc storm_desc: 24 bytes per bank - Total: 191 new banks * 64 bytes = 12224 new bytes Section totals, which include alignment padding: Total global size increase: 11152 bytes of .bss Total per-CPU size increase: 12368 bytes The per-CPU total is replicated for every possible CPU. In the linked image .data..percpu grows by 12352 bytes. The first per-CPU chunk is page aligned, so each CPU retains three more pages, 229376 bytes up from 217088. That is 5.7% more per-CPU memory, or 6 MiB on a 512 thread system. Assisted-by: Claude:claude-opus-5 Signed-off-by: Yazen Ghannam --- arch/x86/include/asm/mce.h | 2 +- arch/x86/kernel/cpu/mce/core.c | 6 ------ arch/x86/kernel/cpu/mce/intel.c | 2 +- 3 files changed, 2 insertions(+), 8 deletions(-) diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index e575b702063d..877641d76efb 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -268,7 +268,7 @@ void mce_log(struct mce_hw_err *err); DECLARE_PER_CPU(struct device *, mce_device); /* Maximum number of MCA banks per CPU. */ -#define MAX_NR_BANKS 64 +#define MAX_NR_BANKS 255 #ifdef CONFIG_X86_MCE_INTEL void mce_intel_feature_init(struct cpuinfo_x86 *c); diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index ab469605fc89..66bc30f2b106 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -1849,12 +1849,6 @@ static void __mcheck_cpu_cap_init(void) b = cap & MCG_BANKCNT_MASK; - if (b > MAX_NR_BANKS) { - pr_warn("CPU%d: Using only %u machine check banks out of %u\n", - smp_processor_id(), MAX_NR_BANKS, b); - b = MAX_NR_BANKS; - } - this_cpu_write(mce_num_banks, b); __mcheck_cpu_mce_banks_init(); diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/intel.c index 4655223ba560..fa63f864e4ad 100644 --- a/arch/x86/kernel/cpu/mce/intel.c +++ b/arch/x86/kernel/cpu/mce/intel.c @@ -95,7 +95,7 @@ static bool cmci_supported(int *banks) return false; rdmsrq(MSR_IA32_MCG_CAP, cap); - *banks = min_t(unsigned, MAX_NR_BANKS, cap & MCG_BANKCNT_MASK); + *banks = this_cpu_read(mce_num_banks); return !!(cap & MCG_CMCI_P); } -- 2.43.0