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Fri, 04 Sep 2026 05:01:32 -0700 (PDT) Received: from volcano9f6e-hostos.amd.com ([165.204.217.251]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-14324356931sm10164241c88.4.2026.09.04.05.01.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Sep 2026 05:01:31 -0700 (PDT) From: Hemanth Selam To: Austin Zheng , Jun Lei , Harry Wentland , Leo Li , Rodrigo Siqueira , Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , David Airlie , Simona Vetter , Kenneth Feng Cc: linux-kernel@vger.kernel.org, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH 2/3] drm/amd: fix repeated words in comments Date: Fri, 4 Sep 2026 17:30:08 +0530 Message-ID: <20260904120044.14303-3-hemanth.selam@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20260904120044.14303-1-hemanth.selam@gmail.com> References: <20260904120044.14303-1-hemanth.selam@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Drop words accidentally written twice, reported by checkpatch.pl as a possible repeated word. Only touches comments, no code changes. Assisted-by: Cursor:claude-opus-5 Signed-off-by: Hemanth Selam --- .../dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c | 2 +- .../dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn5_calcs_dchub.c | 2 +- .../dml21/src/dml2_core/dml2_core_dcn5_calcs_dsc_latency.c | 2 +- .../src/dml2_standalone_libraries/alternate_pstate_shared_lib.c | 2 +- .../gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h | 2 +- .../gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c index 802d060a03ac..75bb237dd5e5 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c @@ -5702,7 +5702,7 @@ static bool CalculatePrefetchSchedule(struct dml2_core_internal_scratch *scratch // vs the latency based number // prefetch_bw1: VM + 2*R0 + SW - // so prefetch_bw1 will have enough bw to transfer the necessary data within Tpre_rounded - Tno_bw (Tpre is the the worst-case latency based time to fetch the data) + // so prefetch_bw1 will have enough bw to transfer the necessary data within Tpre_rounded - Tno_bw (Tpre is the worst-case latency based time to fetch the data) // here is to make sure equ bw wont be more agressive than the latency-based requirement. // check vm time >= vm_trips // check r0 time >= r0_trips diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn5_calcs_dchub.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn5_calcs_dchub.c index fea336d3953d..3b2d8bd85494 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn5_calcs_dchub.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn5_calcs_dchub.c @@ -3167,7 +3167,7 @@ bool dcn5_calculate_prefetch_schedule(struct dml2_core_internal_scratch *scratch // vs the latency based number // prefetch_bw1: VM + 2*R0 + SW - // so prefetch_bw1 will have enough bw to transfer the necessary data within Tpre_rounded - Tno_bw (Tpre is the the worst-case latency based time to fetch the data) + // so prefetch_bw1 will have enough bw to transfer the necessary data within Tpre_rounded - Tno_bw (Tpre is the worst-case latency based time to fetch the data) // here is to make sure equ bw wont be more agressive than the latency-based requirement. // check vm time >= vm_trips // check r0 time >= r0_trips diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn5_calcs_dsc_latency.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn5_calcs_dsc_latency.c index 84eac364222f..e1c13bc40ad7 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn5_calcs_dsc_latency.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn5_calcs_dsc_latency.c @@ -133,7 +133,7 @@ static void dscc_bcl_compute_delay(latency_t *p, int bpc, float bpp, int slice_w //this step is necessary as each padded pixel added takes up a clock cycle but is not included in the initialXmitDelay and, therefore, adds to the overall delay ixd_plus_padding = initial_xmit_delay + slice_padded_pixels * lines_to_reach_ixd; - //convert the the padded initial transmit delay from pixels to groups by rounding up to the nearest group as DSC processes in groups of pixels + //convert the padded initial transmit delay from pixels to groups by rounding up to the nearest group as DSC processes in groups of pixels ixd_plus_padding_groups = (ixd_plus_padding + 2) / 3; //number of groups required for a slice to reach initial transmit delay is the sum of the padded initial transmit delay plus the ssm group priming delay diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_standalone_libraries/alternate_pstate_shared_lib.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_standalone_libraries/alternate_pstate_shared_lib.c index 42af0cbf9516..4ed75444d6e8 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_standalone_libraries/alternate_pstate_shared_lib.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_standalone_libraries/alternate_pstate_shared_lib.c @@ -580,7 +580,7 @@ static void calculate_start_index_num_swaths( * *********************************************************************************************************** * calculate_hubp_start_end_lines: Function that calculates svp parameters given a target p-state line * - * This function calculates the the svp parameters (vp0 and vp1 programming) in terms of swath index and number + * This function calculates the svp parameters (vp0 and vp1 programming) in terms of swath index and number * of swaths given an otg p-state target. This function should be called per plane. There are 5 steps: * * 1. Calculate svp0_start_dst_line and svp0_end_dst_line. diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h index d518dee18e1b..6ba06f2196b6 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h @@ -487,7 +487,7 @@ typedef struct { uint16_t Tvr_socLimit; // Celcius uint32_t FitLimit; // Failures in time (failures per million parts over the defined lifetime) - uint16_t PpmPowerLimit; // Switch this this power limit when temperature is above PpmTempThreshold + uint16_t PpmPowerLimit; // Switch this power limit when temperature is above PpmTempThreshold uint16_t PpmTemperatureThreshold; // SECTION: Throttler settings diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h index c5c1943fb6a1..0b4aa66d1883 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h @@ -545,7 +545,7 @@ typedef struct { uint16_t TplxLimit; // Celcius uint32_t FitLimit; // Failures in time (failures per million parts over the defined lifetime) - uint16_t PpmPowerLimit; // Switch this this power limit when temperature is above PpmTempThreshold + uint16_t PpmPowerLimit; // Switch this power limit when temperature is above PpmTempThreshold uint16_t PpmTemperatureThreshold; // SECTION: Throttler settings -- 2.48.1