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Fri, 04 Sep 2026 11:51:07 -0700 (PDT) X-Received: by 2002:a17:90b:2e0e:b0:398:9be5:b419 with SMTP id 98e67ed59e1d1-39b2622bfecmr12140259a91.20.1788547866683; Fri, 04 Sep 2026 11:51:06 -0700 (PDT) Received: from hu-jkona-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3339b9f68e4sm8682644eec.24.2026.09.04.11.51.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Sep 2026 11:51:06 -0700 (PDT) From: Jagadeesh Kona Date: Sat, 05 Sep 2026 00:20:43 +0530 Subject: [PATCH 2/4] clk: qcom: rpmhcc: Add LNBB clocks support for Glymur Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260905-glymur-ufs-clk-changes-v1-2-cdff2c67a8c2@oss.qualcomm.com> References: <20260905-glymur-ufs-clk-changes-v1-0-cdff2c67a8c2@oss.qualcomm.com> In-Reply-To: <20260905-glymur-ufs-clk-changes-v1-0-cdff2c67a8c2@oss.qualcomm.com> To: Bjorn Andersson , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dmitry Baryshkov , Taniya Das , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jagadeesh Kona X-Mailer: b4 0.14.2 X-Authority-Analysis: v=2.4 cv=baFbluPB c=1 sm=1 tr=0 ts=6a9b131c cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=XYjrdpVuIsIQvarJBHYA:9 a=QEXdDO2ut3YA:10 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-ORIG-GUID: g8RIKn9Pemsx5gqE_3IA-hAKUT8rhSzi X-Proofpoint-GUID: g8RIKn9Pemsx5gqE_3IA-hAKUT8rhSzi X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTA0MDE3MiBTYWx0ZWRfX+oqZkBhuGI8V PVLdPyOoz9Y3H40iMccKZSsTgGNz6xZ/tiTh51Er5AChhl0fcBmH+mZlGFsXezXJG7u91Z8bMMv NAsWQvICzBI1riR11mUCfymUn9y87cHL9qjlx3LXOMvDB29tPUz1XWUaJBGzqIgZ4yI4Gl0fljJ FpRVXDZ79DwqkEGCgN72GqWaBiH5ZpitMyVZlV3CBINR03zMqB9g5Fe0b6Uf4YlToIpGHMalq6S 5uEEFCrNvBtrjWKS9c/nSO4GSFq71U1DbYH/iEVCphAJVKaC0fM8K3IoF3ZxNdQ7uYBpoI6uo+S wrCeYiIXprbqNS9uQET80uiZyhXkhDqcbXympNmk7fuZMvy6pN670pVx2+09HTvV8Jv24p0bYJ3 9BdBxMJol8X6jBb5G/r/50D2DJ7BC+Hx8FJYGa7IVQrMgZHdPEJpnW9vmqWn0M7Ua22Oi5OHbQE gukm+wKpU0wP/XT8u/Q== X-Proofpoint-Spam-Info: AW1haW4tMjYwOTA0MDE3MiBTYWx0ZWRfX8RSbaThn8tSB UuB6HRxOinfNgHQxoPHSFqPXuTCfZLqO/Cp9xuf375WPeaqtqPCioRhaVGFmklIZb/v3tfwQH3T AhfzE8/p1Ikug8lsypSAK13i1/jOvv4= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-04_05,2026-09-03_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 clxscore=1015 spamscore=0 bulkscore=0 lowpriorityscore=0 malwarescore=0 suspectscore=0 impostorscore=0 priorityscore=1501 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609040172 Add support for rpmh LN_BB_CLK2 and LN_BB_CLK3 clocks on Qualcomm Glymur platform. Signed-off-by: Jagadeesh Kona --- drivers/clk/qcom/clk-rpmh.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c index ec8700b6186d8d6dd1911b7a33f086805770284a..3db81c709729b547f288eb10d4aa5dcf63d9e951 100644 --- a/drivers/clk/qcom/clk-rpmh.c +++ b/drivers/clk/qcom/clk-rpmh.c @@ -393,6 +393,7 @@ DEFINE_CLK_RPMH_VRM(clk2, _a1_e0, "C2A_E0", 1); DEFINE_CLK_RPMH_VRM(clk3, _a1_e0, "C3A_E0", 1); DEFINE_CLK_RPMH_VRM(clk4, _a1_e0, "C4A_E0", 1); DEFINE_CLK_RPMH_VRM(clk5, _a1_e0, "C5A_E0", 1); +DEFINE_CLK_RPMH_VRM(clk7, _a1_e0, "C7A_E0", 1); DEFINE_CLK_RPMH_VRM(clk8, _a1_e0, "C8A_E0", 1); DEFINE_CLK_RPMH_VRM(clk3, _a2_e0, "C3A_E0", 2); @@ -902,6 +903,10 @@ static struct clk_hw *glymur_rpmh_clocks[] = { [RPMH_RF_CLK4_A] = &clk_rpmh_clk4_a1_e0_ao.hw, [RPMH_RF_CLK5] = &clk_rpmh_clk5_a1_e0.hw, [RPMH_RF_CLK5_A] = &clk_rpmh_clk5_a1_e0_ao.hw, + [RPMH_LN_BB_CLK2] = &clk_rpmh_clk7_a1_e0.hw, + [RPMH_LN_BB_CLK2_A] = &clk_rpmh_clk7_a1_e0_ao.hw, + [RPMH_LN_BB_CLK3] = &clk_rpmh_clk8_a1_e0.hw, + [RPMH_LN_BB_CLK3_A] = &clk_rpmh_clk8_a1_e0_ao.hw, }; static const struct clk_rpmh_desc clk_rpmh_glymur = { -- 2.34.1