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Mon, 07 Sep 2026 01:26:20 -0700 (PDT) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-33808be8fb2sm3423284eec.14.2026.09.07.01.26.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Sep 2026 01:26:19 -0700 (PDT) From: Taniya Das Subject: [PATCH 0/3] clk: qcom: Add Nord DPRX clock controller support Date: Mon, 07 Sep 2026 13:56:12 +0530 Message-Id: <20260907-nords_dprx-v1-0-d472af3f01b1@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIACR1nmoC/6tWKk4tykwtVrJSqFYqSi3LLM7MzwNyDHUUlJIzE vPSU3UzU4B8JSMDIzMDSwNj3bz8opTi+JSCogpdEyA/xTwxOdnCxFAJqKGgKDUtswJsWHRsbS0 A1/qXEVwAAAA= X-Change-ID: 20260903-nords_dprx-4903d7acc841 To: Bjorn Andersson , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Taniya Das X-Mailer: b4 0.15-dev-aa3f6 X-Proofpoint-GUID: ErvYtAEMAwUW21HoJ6AA0e_bXU_Ykivi X-Proofpoint-ORIG-GUID: ErvYtAEMAwUW21HoJ6AA0e_bXU_Ykivi X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTA3MDA5MCBTYWx0ZWRfX18DZ0Ly6H0J+ r/g/GqjuMjITCyn5V4J2cTsUeavasOGkKqE+NFBq2xdRqEAHFtO5EcnuUe03wmY5USiI8QZo4KG sK5bUE7L6mafykn02l5QIQE5a7W6zKfeHeHGiTKwOq5jPvqou4lFIKfwBWTbA5mkp6dbK4dsLTc jmnsEI6NrZ+A7uROp4UxLJYAdoktBZF8yh0WYWQwEC76cO6FF2u0lsdbBiU5Bfn9KXVSizXCxLF Ighr4ebOYXrXYmzJIzSKm8hLIb2PcwUNWMRXP29BeXZb/fGaErqrZwUKwhfITjHsLzbMWBZjirM qDyZbCdij3vK9Oow9yj8Vtcy28VNMh7Fwoi+C8efdbfMavnYPjGkeeHsM/JC2UQukSxq+yWS06v D5iLvZh6pE3hMNIIbvbhNtnb4GRU24nml8GNW4bXf/X8JLRUO/L5EalcISk7HqTU5DhQKcAGp34 Tca4c/dxqACS2gsCs2w== X-Authority-Analysis: v=2.4 cv=DYgnbPtW c=1 sm=1 tr=0 ts=6a9e752d cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=lgvwsS_33UyABBN7wXAA:9 a=QEXdDO2ut3YA:10 a=bFCP_H2QrGi7Okbo017w:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTA3MDA5MCBTYWx0ZWRfX1L+8r5gmyE8k bTHmiHzr1GqDcX9rDmkT9AMQNmXOFReWGH4YaMhgY7ygyP9/oiGWrVo/gyqBJhtdAyd4f5j+Tp8 2W3GCHLe2C/MDgiFLWAYB+5za/Bhv/I= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-07_02,2026-09-03_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 clxscore=1015 bulkscore=0 suspectscore=0 malwarescore=0 adultscore=0 lowpriorityscore=0 priorityscore=1501 impostorscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609070090 Add support for the DisplayPort Receiver (DPRX) clock controllers found on Qualcomm Nord devices. There are two identical DPRX clock controller instances (DPRX0 and DPRX1), each providing clocks for the DPRX core, audio, AHB and video memory paths, along with their core PLLs. The DPRX PLLs are ZONDA_OLE instances whose PLL_ALPHA_VAL register has been widened to 28 bits to carry the fractional word at a finer resolution. The existing alpha-PLL core derives the ALPHA_VAL width solely from the register-map layout and can only express 16 or 40 bits, so the first patch adds an optional per-PLL alpha_width override that, when set, feeds the recalc_rate/round_rate scaling and the Zonda set_rate L-adjust MSB check. This is a prerequisite for the DPRX PLLs to lock to and report the correct rate. The series is organised as follows: - Patch 1 - alpha-PLL 28-bit ALPHA_VAL width. - Patch 2 - documents the Nord DPRX clock controller device tree bindings. - Patch 3 - adds the two DPRX clock controller drivers. Signed-off-by: Taniya Das --- Taniya Das (3): clk: qcom: clk-alpha-pll: support a 28-bit ALPHA_VAL width dt-bindings: clock: qcom: document the Nord DPRX Clock Controller clk: qcom: dprxcc: Add Nord DPRX clock controller support .../bindings/clock/qcom,nord-dprxcc.yaml | 68 ++++ drivers/clk/qcom/Kconfig | 11 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/clk-alpha-pll.c | 7 +- drivers/clk/qcom/clk-alpha-pll.h | 3 + drivers/clk/qcom/dprxcc0-nord.c | 436 +++++++++++++++++++++ drivers/clk/qcom/dprxcc1-nord.c | 436 +++++++++++++++++++++ include/dt-bindings/clock/qcom,nord-dprxcc.h | 27 ++ 8 files changed, 986 insertions(+), 3 deletions(-) --- base-commit: af5f12805e5cefa4fe68d6127c7e1fb78cd5535c change-id: 20260903-nords_dprx-4903d7acc841 Best regards, -- Taniya Das