From: Yixun Lan <dlan@kernel.org>
To: Troy Mitchell <troy.mitchell@linux.spacemit.com>
Cc: Michael Turquette <mturquette@baylibre.com>,
Inochi Amaoto <inochiama@outlook.com>,
Alex Elder <elder@riscstar.com>, Haylen Chu <heylenay@4d2.org>,
Aurelien Jarno <aurelien@aurel32.net>,
stable@vger.kernel.org,
Anirudh Srinivasan <asrinivasan@oss.tenstorrent.com>,
Stephen Boyd <sboyd@kernel.org>,
Brian Masney <bmasney+clk@redhat.com>,
Jerome Brunet <jbrunet+clk@baylibre.com>,
Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>,
linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org,
spacemit@lists.linux.dev, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v5] clk: spacemit: k3: add CPU PLL rate tables
Date: Mon, 7 Sep 2026 07:43:16 +0000 [thread overview]
Message-ID: <20260907074316-GKC2330@kernel.org> (raw)
In-Reply-To: <20260907-k3-pll5-pll8-1800mhz-v5-1-5cc96d716b0a@linux.spacemit.com>
On 09:54 Mon 07 Sep , Troy Mitchell wrote:
> The K3 CPU PLL rate tables currently describe only one rate per PLL,
> although the hardware supports a wider range.
>
> PLL3 and PLL4 support rates from 1.05 to 2.4 GHz, while PLL5 and PLL8
> support rates from 1.05 to 2 GHz. Populate the tables with every
> supported rate in 50 MHz steps.
>
> Fixes: e371a77255b8 ("clk: spacemit: k3: add the clock tree")
> Cc: stable@vger.kernel.org # 7.0+
> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
> Tested-by: Aurelien Jarno <aurelien@aurel32.net>
> Tested-by: Anirudh Srinivasan <asrinivasan@oss.tenstorrent.com>
> Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com>
Reviewed-by: Yixun Lan <dlan@kernel.org>
--
Yixun Lan (dlan)
prev parent reply other threads:[~2026-09-07 7:43 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-07 1:54 Troy Mitchell
2026-09-07 7:43 ` Yixun Lan [this message]
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