From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5AA4646D2B9; Mon, 7 Sep 2026 09:58:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788775132; cv=none; b=eNl8UMyg36yipJ9f1YHr12g2RoiebDDeWXlgqlnQcOxV+z2KN77/XZcUNR7v384Q1XMfv7Obm5Uyy5BnhvyJSXPB/rbSRJ1TjGNTTRV77ZysV98XJwuXkkOMJHpZfcGpnwjISEVAOvVXZAiiy5EfFEQJY6fg6XOGz/R4vYJcpa8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788775132; c=relaxed/simple; bh=2WSeminL2sHAHn+HbQhaOX4FADTSAQfyN4PN41I4lsw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=g9A5jgw2QeHU86V7RqFd6tUObLof1IeZv8lrIIQLserIo3UR8RmZ/feJc9p5L+6XnnuJYVBE9EvNAzTuRhSJVS94+MlcOn6H7ZCkIh6of7PoBD5EJsXR8nLstoyUpnKNaD9CIC5uFB+RkiXMxyqFF1j8G7cA9XsR+Qtomd8l6Uc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=dbBVeCbr; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="dbBVeCbr" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C011E1F00ACA; Mon, 7 Sep 2026 09:58:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788775130; bh=BqnIWeCAGaPUYlaZlk6L1OPF4VRf6Uq0c3BQIWypxoA=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=dbBVeCbrIiVEQAhhDrY6TpOpojp1xG4UaPfjdNsWtWXQ15rIWEUF6U0z0TtBdWe8v 4zhJHDeIjsxGW9XjgxvMNcCCTdw5uBrCtCGfRyNuWdDtvvtpuTmHTgmpsoDBZcx6E8 uNZH/V2aCqxELC0TmPQMPi5KHcXHgm/YoIQ19lSavpEaJ7N5KG0AuENUpoQgZVQYcB 3CcMTzPdGzqS7QdaZMRuKE6u7OG9Fz4002O0DmkZ817oFM5E0tipqBXs+41MDaQwH0 uM7ejISloEu/d7lUIR+aCxVnkhD8diBfXrhfUqczK+8LPHm+LFHPOpOQVbksrS0mSB lGueKopIbqfqQ== Received: from phl-compute-06.internal (phl-compute-06.internal [10.202.2.46]) by mailfauth.ams.internal (Postfix) with ESMTP id EACA0198003A; Mon, 7 Sep 2026 05:58:46 -0400 (EDT) Received: from phl-frontend-04 ([10.202.2.163]) by phl-compute-06.internal (MEProxy); Mon, 07 Sep 2026 05:58:48 -0400 X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: dmFkZTEfmTDj/r+7N3SoJC/vnCUjsKNijMe1VXFD0b88h55H2gBIFouQJkZSZK1yyk30Sm mIpo4+lqFBdKW9tiCpcqxnDvXOftY/uwGIbts6csXqNfxsNqOfnYnFu40A0wAOj35G9s+w IAMv9bbisiS7ei9Uc4aFfDLSUxZi6vkR+vpXkb8NeS63qvjIFlVzXVDhwHvtwaAOtbHyG2 EUUfEj73JOAPxGIHZGnc8vHsjF2mphj6z1w+QhR+1XLYLXNDi1frGA6EeIrPkmhp8ZYVyp w0DvRbQmjeBcjm+uOYs5drfpJJgg1sHnCQ9G2soFC7z9xfrcgmKRrSpzbA16VZVaATLmjT G3X7mrluRu/OP7GWi6COueqWAS0H3GTAGJ/fm56NGzoGd7yk6zkLuzmNrmSMjr6442CP+y HnlPe3n8Xk+qYwbdJcNYCz0zhVGBp52fzd8usy6Fv9D8UkByjw9bqELipPUY49VIjGJE2y JcYI/8qNW7KnpCpfbw5A/XZmV7qwKjxVYos5Scwlkivj00woZwco40oiQ1DODWrecViyGZ ov5bIFs7u1nvBAMGn0nSs7osJZqBdFI2+Je/NL7bbI8gmBfKSV2p5aE0ilvuAaSk5uQcds Tvsfw7j9v1iyR6EXzbNGjAsmmJ+QAREUZ87tqDPg3s1zIjJQp39uQZ/tNe5A X-ME-Proxy: Feedback-ID: i10464835:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Mon, 7 Sep 2026 05:58:45 -0400 (EDT) From: "Kiryl Shutsemau (Meta)" To: Will Deacon , Robin Murphy , Joerg Roedel , Nicolin Chen Cc: Jason Gunthorpe , Pranjal Shrivastava , Mostafa Saleh , Thierry Reding , Krishna Reddy , Jonathan Hunter , Breno Leitao , Kyle McMartin , Usama Arif , kernel-team@meta.com, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, "Kiryl Shutsemau (Meta)" Subject: [PATCH v5 2/2] iommu/arm-smmu-v3: Default queue depths to one page in a kdump kernel Date: Mon, 7 Sep 2026 10:58:35 +0100 Message-ID: <20260907095835.1233352-3-kas@kernel.org> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260907095835.1233352-1-kas@kernel.org> References: <20260907095835.1233352-1-kas@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit All three queues are sized from the maxima the hardware advertises in IDR1 and allocated at probe, up to 4 MB each on a 4K-page kernel. The capture kernel already disables two of them: arm_smmu_device_reset() drops CR0_EVTQEN and CR0_PRIQEN. It still allocates both at full size. A kdump capture kernel runs from a small crashkernel reservation, and every SMMUv3 instance pays that cost again, up to 12 MB apiece. It goes to queues that either serve the handful of devices used to save the dump or are switched off outright, and it is memory the dump itself needs. Default all three depths to one page worth of entries when is_kdump_kernel(). The queues carry commands and fault records rather than DMA data, so dump throughput is unaffected. A shallower command queue only bounds how many commands may be in flight before a sync, which does not matter for the few devices that save the dump. An explicit cmdq_max_entries still wins, so a capture kernel that wants a deeper command queue can ask for one on the command line. Suggested-by: Kyle McMartin Signed-off-by: Kiryl Shutsemau (Meta) Assisted-by: Claude-Code:claude-opus-5 --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 37 +++++++++++++++++---- 1 file changed, 30 insertions(+), 7 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 4550b1105e9c..67dca0cb487b 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -4424,6 +4424,9 @@ static struct iommu_dirty_ops arm_smmu_dirty_ops = { * @ent_sz_shift: log2 of the queue entry size in bytes * @entries: number of entries to cap the queue at, or zero for the default * + * The default is @ceiling, except in a kdump capture kernel, which defaults to + * one page worth of entries. + * * @entries is rounded down to a power of two and floored at one page, because * coherent DMA is page granular: a shallower queue occupies the same memory as * one that fills the page, and arm_smmu_init_one_queue() stops shrinking at a @@ -4433,11 +4436,32 @@ static u32 arm_smmu_queue_max_n_shift(u32 ceiling, u32 ent_sz_shift, u32 entries) { u32 floor = PAGE_SHIFT - ent_sz_shift; + u32 new_ceiling; - if (!entries) + if (entries) + new_ceiling = max(ilog2(entries), floor); + else if (is_kdump_kernel()) + new_ceiling = floor; + else return ceiling; - return min(ceiling, max(ilog2(entries), floor)); + return min(ceiling, new_ceiling); +} + +static inline u32 arm_smmu_evtq_max_n_shift(u32 ceiling) +{ + /* Capped to ensure natural alignment */ + ceiling = min(EVTQ_MAX_SZ_SHIFT, ceiling); + + return arm_smmu_queue_max_n_shift(ceiling, EVTQ_ENT_SZ_SHIFT, 0); +} + +static inline u32 arm_smmu_priq_max_n_shift(u32 ceiling) +{ + /* Capped to ensure natural alignment */ + ceiling = min(PRIQ_MAX_SZ_SHIFT, ceiling); + + return arm_smmu_queue_max_n_shift(ceiling, PRIQ_ENT_SZ_SHIFT, 0); } /* @@ -5196,7 +5220,6 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu) if (reg & IDR1_ATTR_TYPES_OVR) smmu->features |= ARM_SMMU_FEAT_ATTR_TYPES_OVR; - /* Queue sizes, capped to ensure natural alignment */ smmu->cmdq.q.llq.max_n_shift = arm_smmu_cmdq_max_n_shift(FIELD_GET(IDR1_CMDQS, reg)); if (smmu->cmdq.q.llq.max_n_shift <= ilog2(CMDQ_BATCH_ENTRIES)) { @@ -5211,10 +5234,10 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu) return -ENXIO; } - smmu->evtq.q.llq.max_n_shift = min_t(u32, EVTQ_MAX_SZ_SHIFT, - FIELD_GET(IDR1_EVTQS, reg)); - smmu->priq.q.llq.max_n_shift = min_t(u32, PRIQ_MAX_SZ_SHIFT, - FIELD_GET(IDR1_PRIQS, reg)); + smmu->evtq.q.llq.max_n_shift = + arm_smmu_evtq_max_n_shift(FIELD_GET(IDR1_EVTQS, reg)); + smmu->priq.q.llq.max_n_shift = + arm_smmu_priq_max_n_shift(FIELD_GET(IDR1_PRIQS, reg)); /* SID/SSID sizes */ smmu->ssid_bits = FIELD_GET(IDR1_SSIDSIZE, reg); -- 2.54.0