From: Devendra K Verma <devverma@amd.com>
To: <mani@kernel.org>, <vkoul@kernel.org>, <frank.li@kernel.org>,
<den@valinux.co.jp>
Cc: <dmaengine@vger.kernel.org>, <linux-pci@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <michal.simek@amd.com>,
<devverma@amd.com>
Subject: [PATCH v1 1/2] dmaengine: dw-edma: Macro order as per reg bit position
Date: Mon, 7 Sep 2026 16:24:52 +0530 [thread overview]
Message-ID: <20260907105453.1940646-2-devverma@amd.com> (raw)
In-Reply-To: <20260907105453.1940646-1-devverma@amd.com>
For a register the macros providing masks for bit ranges.
These macros if placed in order provide good view of the bits.
Placed macros in ascending order.
Signed-off-by: Devendra K Verma <devverma@amd.com>
---
drivers/dma/dw-edma/dw-edma-pcie.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c b/drivers/dma/dw-edma/dw-edma-pcie.c
index 9f237ba916de..006dea7d6322 100644
--- a/drivers/dma/dw-edma/dw-edma-pcie.c
+++ b/drivers/dma/dw-edma/dw-edma-pcie.c
@@ -31,8 +31,8 @@
#define DW_PCIE_XILINX_MDB_VSEC_DMA_ID 0x6
#define DW_PCIE_XILINX_MDB_VSEC_ID 0x20
-#define DW_PCIE_XILINX_MDB_VSEC_DMA_BAR GENMASK(10, 8)
#define DW_PCIE_XILINX_MDB_VSEC_DMA_MAP GENMASK(2, 0)
+#define DW_PCIE_XILINX_MDB_VSEC_DMA_BAR GENMASK(10, 8)
#define DW_PCIE_XILINX_MDB_VSEC_DMA_WR_CH GENMASK(9, 0)
#define DW_PCIE_XILINX_MDB_VSEC_DMA_RD_CH GENMASK(25, 16)
--
2.43.0
next prev parent reply other threads:[~2026-09-07 10:55 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-07 10:54 [PATCH v1 0/2] Macro Ordering and Typo Correction Devendra K Verma
2026-09-07 10:54 ` Devendra K Verma [this message]
2026-09-07 10:54 ` [PATCH v1 2/2] dmaengine: dw-edma: IP name corrected under its struct Devendra K Verma
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