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From: Xu Yang <xu.yang_2@oss.nxp.com>
To: vkoul@kernel.org, neil.armstrong@linaro.org, mani@kernel.org,
	dmitry.baryshkov@oss.qualcomm.com, ivo.ivanov.ivanov1@gmail.com
Cc: linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org,
	imx@lists.linux.dev
Subject: [PATCH] phy: phy-snps-eusb2: fix FSEL_48_MHZ_VAL definition
Date: Tue,  8 Sep 2026 16:59:53 +0800	[thread overview]
Message-ID: <20260908085953.3315953-1-xu.yang_2@oss.nxp.com> (raw)

From: Xu Yang <xu.yang_2@nxp.com>

According to Synopsys eUSB2 PHY Databook, FSEL_48_MHZ_VAL should be 0x6
for supported 48 MHz reference clock.

Fixes: c4098f3e6134 ("phy: phy-snps-eusb2: add support for exynos2200")
Cc: stable@vger.kernel.org
Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
---
 drivers/phy/phy-snps-eusb2.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/phy/phy-snps-eusb2.c b/drivers/phy/phy-snps-eusb2.c
index af4fa17ac6cb..3cb18d6ebc1d 100644
--- a/drivers/phy/phy-snps-eusb2.c
+++ b/drivers/phy/phy-snps-eusb2.c
@@ -21,7 +21,7 @@
 #define FSEL_20_MHZ_VAL			(0x1)
 #define FSEL_24_MHZ_VAL			(0x2)
 #define FSEL_26_MHZ_VAL			(0x3)
-#define FSEL_48_MHZ_VAL			(0x2)
+#define FSEL_48_MHZ_VAL			(0x6)
 
 #define EXYNOS_USB_PHY_CFG_PLLCFG0	(0x8)
 #define PHY_CFG_PLL_FB_DIV_19_8_MASK	GENMASK(19, 8)
-- 
2.34.1


             reply	other threads:[~2026-09-08  8:56 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-08  8:59 Xu Yang [this message]
2026-09-08 12:17 ` ivaylo
2026-09-09  2:49   ` Xu Yang
2026-10-12  9:43     ` Manivannan Sadhasivam

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