From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 11614549387; Tue, 8 Sep 2026 15:29:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788881401; cv=none; b=nlcRZewyWOUf3tG1N1pzPs04C3m0+yzRSQqdMoQyLHm2IHyAQ1FVWySQz1F/GY/NydXEXF/hQsY6iQKh57P6gV7KUxagVoei3cqy1lRUs7I7wCUHBCpe5LZ1/vJWhj0UnS/T7C7eM9tOFiShMvTYgX6GWo1Hc6PSIPRGAB7Foh4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788881401; c=relaxed/simple; bh=Qq3Wk4YKlrfxJoEBhEXKjeu42QmTbtRgFhs/6a0Zie0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=XwyKoTuywTg4DwVG2sqXx8Auc702dVXWFM8RkmPNbzopU8M6Z7wDp6V9qGtsZtOvz2ElCnf4h3X30uedtsYjFP0TR3Zx+9qq/VAZfXT3I+VhDETyXpOHZ2SkPJToB2/OU7y0SVYWnbhM4nbuJ5/ps/xg5wzZ9GsXSYm278GWZuA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=CmN6lsxU; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="CmN6lsxU" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2242D1F00A3D; Tue, 8 Sep 2026 15:29:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788881368; bh=KRlTE30nn2xhGfoswlB5RLO5DrQ6Hn06W0UQ4wtHmsI=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=CmN6lsxU3KECj9l1WLywDjtqo0nF5LFxth+5VjtkJar+awR7dyBPoX3eoJ17Tzm5j GfBxTWh5EqcKcg2cSHZaCiweT0iv7MQESa/cXJnK3um3a7Q/9oTJvRUS4X9NzA0EFW eIiDqhpSx4T7vIQ2iqepYOuPVNcGnRAldkjjydSUlBchFxai3sYsnMQWapFHszMcG0 1bHFOwDhrpMtOH6psSY+H1lwzMk0M2p/eB8lHOfV5wxUmxXzjuBSKqZNgkLJ8Gs9X5 TvdnNWlzxzjdwsjgIAv3cqDsJVU1XwFmfcB4hz1594cywgHlBCc6z4ZOVbOAh4zJRo TC0Wr+I4l3iDA== From: Arnd Bergmann To: Krzysztof Kozlowski , Alexandre Belloni , Linus Walleij , Russell King Cc: Drew Fustini , Arnd Bergmann , Rob Herring , Conor Dooley , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Vladimir Zapolskiy , Stefan Agner , Maxime Coquelin , Alexandre Torgue , Aaro Koskinen , Andreas Kemnade , Kevin Hilman , Roger Quadros , Tony Lindgren , Nicolas Ferre , Claudiu Beznea , Andrew Lunn , Sebastian Hesselbarth , Gregory Clement , Robert Jarzmik , Kristoffer Ericson , Ethan Nelson-Moore , Geert Uytterhoeven , Alexander Sverdlin , Shawn Guo , Karl Mehltretter , "David Hildenbrand (Arm)" , Nicolas Pitre , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, imx@lists.linux.dev, linux-stm32@st-md-mailman.stormreply.com, linux-omap@vger.kernel.org, Alexander Clouter , "Jeremy J. Peper" , Damien Le Moal , Niklas Cassel , Ulf Hansson , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Bjorn Helgaas , Vinod Koul , "Rafael J. Wysocki" , Daniel Lezcano , Guenter Roeck , Mark Brown , Bartosz Golaszewski , Thomas Weissschuh , linux-ide@vger.kernel.org, linux-mmc@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, linux-rtc@vger.kernel.org, linux-pm@vger.kernel.org, linux-watchdog@vger.kernel.org, linux-sound@vger.kernel.org, linux-gpio@vger.kernel.org Subject: [PATCH 05/13] ARM: orion/dove/mv78xx0: remove all board files Date: Tue, 8 Sep 2026 17:27:55 +0200 Message-ID: <20260908152808.3928630-6-arnd@kernel.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260908152808.3928630-1-arnd@kernel.org> References: <20260908152808.3928630-1-arnd@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Arnd Bergmann The 'orion' platform is the predecessor to what linux now calls the 'mvebu' line of Marvell SoCs, and originally covered orion5x, mv78xx0, kirkwood, dove and a few others that do not have any upstream support at the moment. Only a few board files remain here, these are the ones left in 2022 board file purge because they had some level of support in Debian or OpenWRT, mostly for commercial NAS or router boxes. This distro support is now gone, and nobody has converted the board files to devicetree, though the orion5x and dove platforms also come with devicetree support for some other machines. Cc: Andrew Lunn Cc: Sebastian Hesselbarth Cc: Gregory Clement Cc: Alexander Clouter Cc: Jeremy J. Peper Cc: Damien Le Moal Cc: Niklas Cassel Cc: Ulf Hansson Cc: Lorenzo Pieralisi Cc: "Krzysztof Wilczyński" Cc: Manivannan Sadhasivam Cc: Rob Herring Cc: Bjorn Helgaas Cc: Vinod Koul Cc: Alexandre Belloni Cc: "Rafael J. Wysocki" Cc: Daniel Lezcano Cc: Guenter Roeck Cc: Mark Brown Cc: Linus Walleij Cc: Bartosz Golaszewski Cc: Thomas Weissschuh Cc: linux-ide@vger.kernel.org Cc: linux-mmc@vger.kernel.org Cc: linux-pci@vger.kernel.org Cc: linux-phy@lists.infradead.org Cc: linux-rtc@vger.kernel.org Cc: linux-pm@vger.kernel.org Cc: linux-watchdog@vger.kernel.org Cc: linux-sound@vger.kernel.org Cc: linux-gpio@vger.kernel.org Signed-off-by: Arnd Bergmann --- MAINTAINERS | 2 - arch/arm/Kconfig | 2 - arch/arm/Kconfig.debug | 2 +- arch/arm/Makefile | 2 - arch/arm/configs/dove_defconfig | 134 --- arch/arm/configs/mv78xx0_defconfig | 120 --- arch/arm/mach-dove/Kconfig | 32 - arch/arm/mach-dove/Makefile | 7 - arch/arm/mach-dove/bridge-regs.h | 50 -- arch/arm/mach-dove/cm-a510.c | 94 -- arch/arm/mach-dove/common.c | 449 ---------- arch/arm/mach-dove/common.h | 46 - arch/arm/mach-dove/dove.h | 185 ---- arch/arm/mach-dove/irq.c | 81 -- arch/arm/mach-dove/irqs.h | 89 -- arch/arm/mach-dove/mpp.c | 159 ---- arch/arm/mach-dove/mpp.h | 197 ----- arch/arm/mach-dove/pcie.c | 226 ----- arch/arm/mach-dove/pm.h | 58 -- arch/arm/mach-mv78xx0/Kconfig | 27 - arch/arm/mach-mv78xx0/Makefile | 5 - arch/arm/mach-mv78xx0/bridge-regs.h | 31 - arch/arm/mach-mv78xx0/buffalo-wxl-setup.c | 183 ---- arch/arm/mach-mv78xx0/common.c | 444 ---------- arch/arm/mach-mv78xx0/common.h | 54 -- arch/arm/mach-mv78xx0/irq.c | 69 -- arch/arm/mach-mv78xx0/irqs.h | 87 -- arch/arm/mach-mv78xx0/mpp.c | 34 - arch/arm/mach-mv78xx0/mpp.h | 337 ------- arch/arm/mach-mv78xx0/mv78xx0.h | 134 --- arch/arm/mach-mv78xx0/pcie.c | 280 ------ arch/arm/mach-orion5x/Kconfig | 95 -- arch/arm/mach-orion5x/Makefile | 9 - arch/arm/mach-orion5x/board-dt.c | 3 +- arch/arm/mach-orion5x/common.c | 238 +---- arch/arm/mach-orion5x/common.h | 15 - arch/arm/mach-orion5x/dns323-setup.c | 757 ---------------- arch/arm/mach-orion5x/kurobox_pro-setup.c | 407 --------- arch/arm/mach-orion5x/mv2120-setup.c | 256 ------ arch/arm/mach-orion5x/net2big-setup.c | 444 ---------- arch/arm/mach-orion5x/pci.c | 1 - .../arm/mach-orion5x/terastation_pro2-setup.c | 366 -------- arch/arm/mach-orion5x/ts209-setup.c | 331 ------- arch/arm/mach-orion5x/ts409-setup.c | 329 ------- arch/arm/mach-orion5x/ts78xx-fpga.h | 42 - arch/arm/mach-orion5x/ts78xx-setup.c | 574 ------------ arch/arm/mach-orion5x/tsx09-common.c | 129 --- arch/arm/mach-orion5x/tsx09-common.h | 21 - arch/arm/mm/Kconfig | 2 +- arch/arm/plat-orion/Makefile | 2 +- arch/arm/plat-orion/common.c | 826 ------------------ arch/arm/plat-orion/include/plat/addr-map.h | 54 -- arch/arm/plat-orion/include/plat/common.h | 104 --- arch/arm/plat-orion/include/plat/time.h | 20 - arch/arm/plat-orion/pcie.c | 1 - arch/arm/plat-orion/time.c | 238 ----- drivers/ata/Kconfig | 3 +- drivers/mmc/host/Kconfig | 2 +- drivers/pci/controller/Kconfig | 2 +- drivers/phy/marvell/Kconfig | 2 +- drivers/rtc/Kconfig | 2 +- drivers/soc/Makefile | 1 - drivers/thermal/Kconfig | 2 +- drivers/watchdog/Kconfig | 2 +- sound/soc/kirkwood/Kconfig | 2 +- 65 files changed, 14 insertions(+), 8888 deletions(-) delete mode 100644 arch/arm/configs/dove_defconfig delete mode 100644 arch/arm/configs/mv78xx0_defconfig delete mode 100644 arch/arm/mach-dove/Kconfig delete mode 100644 arch/arm/mach-dove/Makefile delete mode 100644 arch/arm/mach-dove/bridge-regs.h delete mode 100644 arch/arm/mach-dove/cm-a510.c delete mode 100644 arch/arm/mach-dove/common.c delete mode 100644 arch/arm/mach-dove/common.h delete mode 100644 arch/arm/mach-dove/dove.h delete mode 100644 arch/arm/mach-dove/irq.c delete mode 100644 arch/arm/mach-dove/irqs.h delete mode 100644 arch/arm/mach-dove/mpp.c delete mode 100644 arch/arm/mach-dove/mpp.h delete mode 100644 arch/arm/mach-dove/pcie.c delete mode 100644 arch/arm/mach-dove/pm.h delete mode 100644 arch/arm/mach-mv78xx0/Kconfig delete mode 100644 arch/arm/mach-mv78xx0/Makefile delete mode 100644 arch/arm/mach-mv78xx0/bridge-regs.h delete mode 100644 arch/arm/mach-mv78xx0/buffalo-wxl-setup.c delete mode 100644 arch/arm/mach-mv78xx0/common.c delete mode 100644 arch/arm/mach-mv78xx0/common.h delete mode 100644 arch/arm/mach-mv78xx0/irq.c delete mode 100644 arch/arm/mach-mv78xx0/irqs.h delete mode 100644 arch/arm/mach-mv78xx0/mpp.c delete mode 100644 arch/arm/mach-mv78xx0/mpp.h delete mode 100644 arch/arm/mach-mv78xx0/mv78xx0.h delete mode 100644 arch/arm/mach-mv78xx0/pcie.c delete mode 100644 arch/arm/mach-orion5x/dns323-setup.c delete mode 100644 arch/arm/mach-orion5x/kurobox_pro-setup.c delete mode 100644 arch/arm/mach-orion5x/mv2120-setup.c delete mode 100644 arch/arm/mach-orion5x/net2big-setup.c delete mode 100644 arch/arm/mach-orion5x/terastation_pro2-setup.c delete mode 100644 arch/arm/mach-orion5x/ts209-setup.c delete mode 100644 arch/arm/mach-orion5x/ts409-setup.c delete mode 100644 arch/arm/mach-orion5x/ts78xx-fpga.h delete mode 100644 arch/arm/mach-orion5x/ts78xx-setup.c delete mode 100644 arch/arm/mach-orion5x/tsx09-common.c delete mode 100644 arch/arm/mach-orion5x/tsx09-common.h delete mode 100644 arch/arm/plat-orion/common.c delete mode 100644 arch/arm/plat-orion/include/plat/addr-map.h delete mode 100644 arch/arm/plat-orion/include/plat/common.h delete mode 100644 arch/arm/plat-orion/include/plat/time.h delete mode 100644 arch/arm/plat-orion/time.c diff --git a/MAINTAINERS b/MAINTAINERS index 6e8fe7640064..028db7ad15ad 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3080,8 +3080,6 @@ F: Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.yaml F: Documentation/devicetree/bindings/soc/dove/ F: arch/arm/boot/dts/marvell/dove* F: arch/arm/boot/dts/marvell/orion5x* -F: arch/arm/mach-dove/ -F: arch/arm/mach-mv78xx0/ F: arch/arm/mach-orion5x/ F: arch/arm/plat-orion/ F: drivers/bus/mvebu-mbus.c diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 5770deca136d..da29afce309f 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -393,8 +393,6 @@ source "arch/arm/mach-mmp/Kconfig" source "arch/arm/mach-mstar/Kconfig" -source "arch/arm/mach-mv78xx0/Kconfig" - source "arch/arm/mach-mvebu/Kconfig" source "arch/arm/mach-mxs/Kconfig" diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 56c090840c5a..e2fc89055463 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -583,7 +583,7 @@ choice config DEBUG_MVEBU_UART0_ALTERNATE bool "Kernel low-level debugging messages via MVEBU UART0 (new bootloaders)" - depends on ARCH_MVEBU || ARCH_DOVE || ARCH_MV78XX0 || ARCH_ORION5X + depends on ARCH_MVEBU || ARCH_ORION5X select DEBUG_UART_8250 help Say Y here if you want kernel low-level debugging support diff --git a/arch/arm/Makefile b/arch/arm/Makefile index f5bc9ad7f6f5..5421a3ec3825 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -179,7 +179,6 @@ machine-$(CONFIG_ARCH_BERLIN) += berlin machine-$(CONFIG_ARCH_CLPS711X) += clps711x machine-$(CONFIG_ARCH_DAVINCI) += davinci machine-$(CONFIG_ARCH_DIGICOLOR) += digicolor -machine-$(CONFIG_ARCH_DOVE) += dove machine-$(CONFIG_ARCH_EXYNOS) += exynos machine-$(CONFIG_ARCH_GEMINI) += gemini machine-$(CONFIG_ARCH_HIGHBANK) += highbank @@ -190,7 +189,6 @@ machine-$(CONFIG_ARCH_LPC18XX) += lpc18xx machine-$(CONFIG_ARCH_LPC32XX) += lpc32xx machine-$(CONFIG_ARCH_MESON) += meson machine-$(CONFIG_ARCH_MMP) += mmp -machine-$(CONFIG_ARCH_MV78XX0) += mv78xx0 machine-$(CONFIG_ARCH_MVEBU) += mvebu machine-$(CONFIG_ARCH_MXC) += imx machine-$(CONFIG_ARCH_MEDIATEK) += mediatek diff --git a/arch/arm/configs/dove_defconfig b/arch/arm/configs/dove_defconfig deleted file mode 100644 index 917a864fec74..000000000000 --- a/arch/arm/configs/dove_defconfig +++ /dev/null @@ -1,134 +0,0 @@ -CONFIG_SYSVIPC=y -CONFIG_NO_HZ_IDLE=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_EXPERT=y -# CONFIG_ARCH_MULTI_V6 is not set -CONFIG_ARCH_MULTI_V7=y -CONFIG_ARCH_DOVE=y -CONFIG_MACH_CM_A510=y -CONFIG_HIGHMEM=y -CONFIG_ATAGS=y -CONFIG_ARM_APPENDED_DTB=y -CONFIG_ARM_ATAG_DTB_COMPAT=y -CONFIG_VFP=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IPV6 is not set -CONFIG_PCI=y -CONFIG_PCI_MSI=y -CONFIG_PCI_MVEBU=y -CONFIG_DEVTMPFS=y -CONFIG_DEVTMPFS_MOUNT=y -CONFIG_MTD=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_JEDECPROBE=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_GEOMETRY=y -# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_CFI_STAA=y -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_M25P80=y -CONFIG_MTD_SPI_NOR=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=1 -# CONFIG_SCSI_PROC_FS is not set -CONFIG_BLK_DEV_SD=y -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_SCSI_LOWLEVEL is not set -CONFIG_ATA=y -CONFIG_SATA_MV=y -CONFIG_NETDEVICES=y -CONFIG_MV643XX_ETH=y -# CONFIG_INPUT_MOUSEDEV is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_KEYBOARD_ATKBD is not set -# CONFIG_MOUSE_PS2 is not set -# CONFIG_SERIO is not set -CONFIG_LEGACY_PTY_COUNT=16 -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_RUNTIME_UARTS=2 -CONFIG_SERIAL_OF_PLATFORM=y -# CONFIG_HW_RANDOM is not set -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_MV64XXX=y -CONFIG_SPI=y -CONFIG_SPI_ORION=y -# CONFIG_HWMON is not set -CONFIG_THERMAL=y -CONFIG_DOVE_THERMAL=y -CONFIG_WATCHDOG=y -CONFIG_ORION_WATCHDOG=y -CONFIG_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_ROOT_HUB_TT=y -CONFIG_USB_STORAGE=y -CONFIG_MMC=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_MMC_SDHCI_DOVE=y -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y -CONFIG_LEDS_GPIO=y -CONFIG_LEDS_TRIGGERS=y -CONFIG_LEDS_TRIGGER_TIMER=y -CONFIG_LEDS_TRIGGER_HEARTBEAT=y -CONFIG_LEDS_TRIGGER_DEFAULT_ON=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_MV=y -CONFIG_DMADEVICES=y -CONFIG_MV_XOR=y -CONFIG_EXT2_FS=y -CONFIG_EXT4_FS=y -# CONFIG_EXT4_FS_XATTR is not set -CONFIG_ISO9660_FS=y -CONFIG_JOLIET=y -CONFIG_UDF_FS=m -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=y -CONFIG_NFS_FS=y -CONFIG_ROOT_NFS=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_CODEPAGE_850=y -CONFIG_NLS_ISO8859_1=y -CONFIG_NLS_ISO8859_2=y -CONFIG_NLS_UTF8=y -CONFIG_TIMER_STATS=y -CONFIG_CRYPTO_NULL=y -CONFIG_CRYPTO_BLOWFISH=y -CONFIG_CRYPTO_TEA=y -CONFIG_CRYPTO_TWOFISH=y -CONFIG_CRYPTO_ECB=m -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_MD4=y -CONFIG_CRYPTO_SHA1=y -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_SHA512=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_DEV_MARVELL_CESA=y -CONFIG_PRINTK_TIME=y -# CONFIG_DEBUG_BUGVERBOSE is not set -CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_FS=y -# CONFIG_SCHED_DEBUG is not set -CONFIG_DEBUG_USER=y diff --git a/arch/arm/configs/mv78xx0_defconfig b/arch/arm/configs/mv78xx0_defconfig deleted file mode 100644 index e3cc8de7c1c2..000000000000 --- a/arch/arm/configs/mv78xx0_defconfig +++ /dev/null @@ -1,120 +0,0 @@ -CONFIG_SYSVIPC=y -CONFIG_NO_HZ_IDLE=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_PREEMPT=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_EXPERT=y -CONFIG_KALLSYMS_ALL=y -CONFIG_PROFILING=y -CONFIG_ARCH_MULTI_V5=y -# CONFIG_ARCH_MULTI_V6 is not set -# CONFIG_ARCH_MULTI_V7 is not set -CONFIG_ARCH_MV78XX0=y -CONFIG_MACH_TERASTATION_WXL=y -CONFIG_HIGHMEM=y -CONFIG_ATAGS=y -CONFIG_VFP=y -CONFIG_KPROBES=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_BSD_DISKLABEL=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IPV6 is not set -CONFIG_NET_PKTGEN=m -CONFIG_MTD=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_JEDECPROBE=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_GEOMETRY=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_CFI_AMDSTD=y -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MTD_NAND_ORION=y -CONFIG_BLK_DEV_LOOP=y -# CONFIG_SCSI_PROC_FS is not set -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_DEV_SR=m -CONFIG_CHR_DEV_SG=m -# CONFIG_BLK_DEV_BSG is not set -CONFIG_ATA=y -CONFIG_SATA_MV=y -CONFIG_NETDEVICES=y -CONFIG_MII=y -CONFIG_NET_PCI=y -CONFIG_MV643XX_ETH=y -# CONFIG_INPUT_MOUSEDEV is not set -CONFIG_MARVELL_PHY=y -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set -# CONFIG_VT is not set -CONFIG_LEGACY_PTY_COUNT=16 -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -# CONFIG_SERIAL_8250_PCI is not set -CONFIG_SERIAL_8250_RUNTIME_UARTS=2 -# CONFIG_HW_RANDOM is not set -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_MV64XXX=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_ROOT_HUB_TT=y -CONFIG_USB_EHCI_TT_NEWSCHED=y -CONFIG_USB_PRINTER=y -CONFIG_USB_STORAGE=y -CONFIG_USB_STORAGE_DATAFAB=y -CONFIG_USB_STORAGE_FREECOM=y -CONFIG_USB_STORAGE_SDDR09=y -CONFIG_USB_STORAGE_SDDR55=y -CONFIG_USB_STORAGE_JUMPSHOT=y -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y -CONFIG_LEDS_TRIGGERS=y -CONFIG_LEDS_TRIGGER_TIMER=y -CONFIG_LEDS_TRIGGER_HEARTBEAT=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_DS1307=y -CONFIG_RTC_DRV_RS5C372=y -CONFIG_RTC_DRV_M41T80=y -CONFIG_EXT2_FS=y -CONFIG_EXT4_FS=y -# CONFIG_EXT4_FS_XATTR is not set -CONFIG_ISO9660_FS=m -CONFIG_JOLIET=y -CONFIG_UDF_FS=m -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=y -CONFIG_CRAMFS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_ROOT_NFS=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_CODEPAGE_850=y -CONFIG_NLS_ISO8859_1=y -CONFIG_NLS_ISO8859_2=y -CONFIG_CRYPTO_CBC=m -CONFIG_CRYPTO_ECB=m -# CONFIG_DEBUG_BUGVERBOSE is not set -CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_FS=y -CONFIG_DEBUG_KERNEL=y -# CONFIG_SLUB_DEBUG is not set -CONFIG_SCHEDSTATS=y -CONFIG_DEBUG_USER=y -CONFIG_DEBUG_LL=y diff --git a/arch/arm/mach-dove/Kconfig b/arch/arm/mach-dove/Kconfig deleted file mode 100644 index f547120e223e..000000000000 --- a/arch/arm/mach-dove/Kconfig +++ /dev/null @@ -1,32 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -menuconfig ARCH_DOVE - bool "Marvell Dove (DEPRECATED)" if ARCH_MULTI_V7 - depends on ATAGS - select CPU_PJ4 - select GPIOLIB - select MVEBU_MBUS - select PINCTRL - select PINCTRL_DOVE - select PLAT_ORION_LEGACY - select PM_GENERIC_DOMAINS if PM - select PCI_QUIRKS if PCI - help - Support for the Marvell Dove SoC 88AP510 using board files. - - Support for this machine will be removed in early 2027, unless - there is a strong reason to keep it. Users should migrate to - the devicetree-enabled version (CONFIG_MACH_DOVE) instead. - -if ARCH_DOVE - -config DOVE_LEGACY - bool - -config MACH_CM_A510 - bool "CompuLab CM-A510 Board" - select DOVE_LEGACY - help - Say 'Y' here if you want your kernel to support the - CompuLab CM-A510 Board. - -endif diff --git a/arch/arm/mach-dove/Makefile b/arch/arm/mach-dove/Makefile deleted file mode 100644 index 0d31390be069..000000000000 --- a/arch/arm/mach-dove/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -ccflags-y := -I$(srctree)/arch/arm/plat-orion/include - -obj-y += common.o -obj-$(CONFIG_DOVE_LEGACY) += irq.o mpp.o -obj-$(CONFIG_PCI) += pcie.o -obj-$(CONFIG_MACH_CM_A510) += cm-a510.o diff --git a/arch/arm/mach-dove/bridge-regs.h b/arch/arm/mach-dove/bridge-regs.h deleted file mode 100644 index 6fbc152d0950..000000000000 --- a/arch/arm/mach-dove/bridge-regs.h +++ /dev/null @@ -1,50 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* Mbus-L to Mbus Bridge Registers */ - -#ifndef __ASM_ARCH_BRIDGE_REGS_H -#define __ASM_ARCH_BRIDGE_REGS_H - -#include "dove.h" - -#define CPU_CONFIG (BRIDGE_VIRT_BASE + 0x0000) - -#define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104) -#define CPU_CTRL_PCIE0_LINK 0x00000001 -#define CPU_RESET 0x00000002 -#define CPU_CTRL_PCIE1_LINK 0x00000008 - -#define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108) -#define RSTOUTn_MASK_PHYS (BRIDGE_PHYS_BASE + 0x0108) -#define SOFT_RESET_OUT_EN 0x00000004 - -#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c) -#define SOFT_RESET 0x00000001 - -#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE + 0x0110) -#define BRIDGE_INT_TIMER1_CLR (~0x0004) - -#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200) -#define IRQ_CAUSE_LOW_OFF 0x0000 -#define IRQ_MASK_LOW_OFF 0x0004 -#define FIQ_MASK_LOW_OFF 0x0008 -#define ENDPOINT_MASK_LOW_OFF 0x000c -#define IRQ_CAUSE_HIGH_OFF 0x0010 -#define IRQ_MASK_HIGH_OFF 0x0014 -#define FIQ_MASK_HIGH_OFF 0x0018 -#define ENDPOINT_MASK_HIGH_OFF 0x001c -#define PCIE_INTERRUPT_MASK_OFF 0x0020 - -#define IRQ_MASK_LOW (IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF) -#define FIQ_MASK_LOW (IRQ_VIRT_BASE + FIQ_MASK_LOW_OFF) -#define ENDPOINT_MASK_LOW (IRQ_VIRT_BASE + ENDPOINT_MASK_LOW_OFF) -#define IRQ_MASK_HIGH (IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF) -#define FIQ_MASK_HIGH (IRQ_VIRT_BASE + FIQ_MASK_HIGH_OFF) -#define ENDPOINT_MASK_HIGH (IRQ_VIRT_BASE + ENDPOINT_MASK_HIGH_OFF) -#define PCIE_INTERRUPT_MASK (IRQ_VIRT_BASE + PCIE_INTERRUPT_MASK_OFF) - -#define POWER_MANAGEMENT (BRIDGE_VIRT_BASE + 0x011c) - -#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300) -#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE + 0x0300) - -#endif diff --git a/arch/arm/mach-dove/cm-a510.c b/arch/arm/mach-dove/cm-a510.c deleted file mode 100644 index beb532537c22..000000000000 --- a/arch/arm/mach-dove/cm-a510.c +++ /dev/null @@ -1,94 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * arch/arm/mach-dove/cm-a510.c - * - * Copyright (C) 2010 CompuLab, Ltd. - * Konstantin Sinyuk - * - * Based on Marvell DB-MV88AP510-BP Development Board Setup - */ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include "dove.h" -#include "common.h" - -static struct mv643xx_eth_platform_data cm_a510_ge00_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR_DEFAULT, -}; - -static struct mv_sata_platform_data cm_a510_sata_data = { - .n_ports = 1, -}; - -/* - * SPI Devices: - * SPI0: 1M Flash Winbond w25q32bv - */ -static const struct flash_platform_data cm_a510_spi_flash_data = { - .type = "w25q32bv", -}; - -static struct spi_board_info __initdata cm_a510_spi_flash_info[] = { - { - .modalias = "m25p80", - .platform_data = &cm_a510_spi_flash_data, - .irq = -1, - .max_speed_hz = 20000000, - .bus_num = 0, - .chip_select = 0, - }, -}; - -static int __init cm_a510_pci_init(void) -{ - if (machine_is_cm_a510()) - dove_pcie_init(1, 1); - - return 0; -} - -subsys_initcall(cm_a510_pci_init); - -/* Board Init */ -static void __init cm_a510_init(void) -{ - /* - * Basic Dove setup. Needs to be called early. - */ - dove_init(); - - dove_ge00_init(&cm_a510_ge00_data); - dove_ehci0_init(); - dove_ehci1_init(); - dove_sata_init(&cm_a510_sata_data); - dove_sdio0_init(); - dove_sdio1_init(); - dove_spi0_init(); - dove_spi1_init(); - dove_uart0_init(); - dove_uart1_init(); - dove_i2c_init(); - spi_register_board_info(cm_a510_spi_flash_info, - ARRAY_SIZE(cm_a510_spi_flash_info)); -} - -MACHINE_START(CM_A510, "Compulab CM-A510 Board") - .atag_offset = 0x100, - .nr_irqs = DOVE_NR_IRQS, - .init_machine = cm_a510_init, - .map_io = dove_map_io, - .init_early = dove_init_early, - .init_irq = dove_init_irq, - .init_time = dove_timer_init, - .restart = dove_restart, -MACHINE_END diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c deleted file mode 100644 index 35e978514591..000000000000 --- a/arch/arm/mach-dove/common.c +++ /dev/null @@ -1,449 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * arch/arm/mach-dove/common.c - * - * Core functions for Marvell Dove 88AP510 System On Chip - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "bridge-regs.h" -#include "pm.h" -#include "common.h" - -/* These can go away once Dove uses the mvebu-mbus DT binding */ -#define DOVE_MBUS_PCIE0_MEM_TARGET 0x4 -#define DOVE_MBUS_PCIE0_MEM_ATTR 0xe8 -#define DOVE_MBUS_PCIE0_IO_TARGET 0x4 -#define DOVE_MBUS_PCIE0_IO_ATTR 0xe0 -#define DOVE_MBUS_PCIE1_MEM_TARGET 0x8 -#define DOVE_MBUS_PCIE1_MEM_ATTR 0xe8 -#define DOVE_MBUS_PCIE1_IO_TARGET 0x8 -#define DOVE_MBUS_PCIE1_IO_ATTR 0xe0 -#define DOVE_MBUS_CESA_TARGET 0x3 -#define DOVE_MBUS_CESA_ATTR 0x1 -#define DOVE_MBUS_BOOTROM_TARGET 0x1 -#define DOVE_MBUS_BOOTROM_ATTR 0xfd -#define DOVE_MBUS_SCRATCHPAD_TARGET 0xd -#define DOVE_MBUS_SCRATCHPAD_ATTR 0x0 - -/***************************************************************************** - * I/O Address Mapping - ****************************************************************************/ -static struct map_desc __maybe_unused dove_io_desc[] __initdata = { - { - .virtual = (unsigned long) DOVE_SB_REGS_VIRT_BASE, - .pfn = __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE), - .length = DOVE_SB_REGS_SIZE, - .type = MT_DEVICE, - }, { - .virtual = (unsigned long) DOVE_NB_REGS_VIRT_BASE, - .pfn = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE), - .length = DOVE_NB_REGS_SIZE, - .type = MT_DEVICE, - }, -}; - -void __init dove_map_io(void) -{ - iotable_init(dove_io_desc, ARRAY_SIZE(dove_io_desc)); -} - -/***************************************************************************** - * CLK tree - ****************************************************************************/ -static int dove_tclk; - -static DEFINE_SPINLOCK(gating_lock); -static struct clk *tclk; - -static struct clk __init *dove_register_gate(const char *name, - const char *parent, u8 bit_idx) -{ - return clk_register_gate(NULL, name, parent, 0, - (void __iomem *)CLOCK_GATING_CONTROL, - bit_idx, 0, &gating_lock); -} - -static void __init dove_clk_init(void) -{ - struct clk *usb0, *usb1, *sata, *pex0, *pex1, *sdio0, *sdio1; - struct clk *nand, *camera, *i2s0, *i2s1, *crypto, *ac97, *pdma; - struct clk *xor0, *xor1, *ge; - - tclk = clk_register_fixed_rate(NULL, "tclk", NULL, 0, dove_tclk); - - usb0 = dove_register_gate("usb0", "tclk", CLOCK_GATING_BIT_USB0); - usb1 = dove_register_gate("usb1", "tclk", CLOCK_GATING_BIT_USB1); - sata = dove_register_gate("sata", "tclk", CLOCK_GATING_BIT_SATA); - pex0 = dove_register_gate("pex0", "tclk", CLOCK_GATING_BIT_PCIE0); - pex1 = dove_register_gate("pex1", "tclk", CLOCK_GATING_BIT_PCIE1); - sdio0 = dove_register_gate("sdio0", "tclk", CLOCK_GATING_BIT_SDIO0); - sdio1 = dove_register_gate("sdio1", "tclk", CLOCK_GATING_BIT_SDIO1); - nand = dove_register_gate("nand", "tclk", CLOCK_GATING_BIT_NAND); - camera = dove_register_gate("camera", "tclk", CLOCK_GATING_BIT_CAMERA); - i2s0 = dove_register_gate("i2s0", "tclk", CLOCK_GATING_BIT_I2S0); - i2s1 = dove_register_gate("i2s1", "tclk", CLOCK_GATING_BIT_I2S1); - crypto = dove_register_gate("crypto", "tclk", CLOCK_GATING_BIT_CRYPTO); - ac97 = dove_register_gate("ac97", "tclk", CLOCK_GATING_BIT_AC97); - pdma = dove_register_gate("pdma", "tclk", CLOCK_GATING_BIT_PDMA); - xor0 = dove_register_gate("xor0", "tclk", CLOCK_GATING_BIT_XOR0); - xor1 = dove_register_gate("xor1", "tclk", CLOCK_GATING_BIT_XOR1); - dove_register_gate("gephy", "tclk", CLOCK_GATING_BIT_GIGA_PHY); - ge = dove_register_gate("ge", "gephy", CLOCK_GATING_BIT_GBE); - - orion_clkdev_add(NULL, "orion_spi.0", tclk); - orion_clkdev_add(NULL, "orion_spi.1", tclk); - orion_clkdev_add(NULL, "orion_wdt", tclk); - orion_clkdev_add(NULL, "mv64xxx_i2c.0", tclk); - - orion_clkdev_add(NULL, "orion-ehci.0", usb0); - orion_clkdev_add(NULL, "orion-ehci.1", usb1); - orion_clkdev_add(NULL, "mv643xx_eth_port.0", ge); - orion_clkdev_add(NULL, "sata_mv.0", sata); - orion_clkdev_add("0", "pcie", pex0); - orion_clkdev_add("1", "pcie", pex1); - orion_clkdev_add(NULL, "sdhci-dove.0", sdio0); - orion_clkdev_add(NULL, "sdhci-dove.1", sdio1); - orion_clkdev_add(NULL, "orion_nand", nand); - orion_clkdev_add(NULL, "cafe1000-ccic.0", camera); - orion_clkdev_add(NULL, "mvebu-audio.0", i2s0); - orion_clkdev_add(NULL, "mvebu-audio.1", i2s1); - orion_clkdev_add(NULL, "mv_crypto", crypto); - orion_clkdev_add(NULL, "dove-ac97", ac97); - orion_clkdev_add(NULL, "dove-pdma", pdma); - orion_clkdev_add(NULL, MV_XOR_NAME ".0", xor0); - orion_clkdev_add(NULL, MV_XOR_NAME ".1", xor1); -} - -/***************************************************************************** - * EHCI0 - ****************************************************************************/ -void __init dove_ehci0_init(void) -{ - orion_ehci_init(DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0, EHCI_PHY_NA); -} - -/***************************************************************************** - * EHCI1 - ****************************************************************************/ -void __init dove_ehci1_init(void) -{ - orion_ehci_1_init(DOVE_USB1_PHYS_BASE, IRQ_DOVE_USB1); -} - -/***************************************************************************** - * GE00 - ****************************************************************************/ -void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data) -{ - orion_ge00_init(eth_data, DOVE_GE00_PHYS_BASE, - IRQ_DOVE_GE00_SUM, IRQ_DOVE_GE00_ERR, - 1600); -} - -/***************************************************************************** - * SoC RTC - ****************************************************************************/ -static void __init dove_rtc_init(void) -{ - orion_rtc_init(DOVE_RTC_PHYS_BASE, IRQ_DOVE_RTC); -} - -/***************************************************************************** - * SATA - ****************************************************************************/ -void __init dove_sata_init(struct mv_sata_platform_data *sata_data) -{ - orion_sata_init(sata_data, DOVE_SATA_PHYS_BASE, IRQ_DOVE_SATA); - -} - -/***************************************************************************** - * UART0 - ****************************************************************************/ -void __init dove_uart0_init(void) -{ - orion_uart0_init(DOVE_UART0_VIRT_BASE, DOVE_UART0_PHYS_BASE, - IRQ_DOVE_UART_0, tclk); -} - -/***************************************************************************** - * UART1 - ****************************************************************************/ -void __init dove_uart1_init(void) -{ - orion_uart1_init(DOVE_UART1_VIRT_BASE, DOVE_UART1_PHYS_BASE, - IRQ_DOVE_UART_1, tclk); -} - -/***************************************************************************** - * UART2 - ****************************************************************************/ -void __init dove_uart2_init(void) -{ - orion_uart2_init(DOVE_UART2_VIRT_BASE, DOVE_UART2_PHYS_BASE, - IRQ_DOVE_UART_2, tclk); -} - -/***************************************************************************** - * UART3 - ****************************************************************************/ -void __init dove_uart3_init(void) -{ - orion_uart3_init(DOVE_UART3_VIRT_BASE, DOVE_UART3_PHYS_BASE, - IRQ_DOVE_UART_3, tclk); -} - -/***************************************************************************** - * SPI - ****************************************************************************/ -void __init dove_spi0_init(void) -{ - orion_spi_init(DOVE_SPI0_PHYS_BASE); -} - -void __init dove_spi1_init(void) -{ - orion_spi_1_init(DOVE_SPI1_PHYS_BASE); -} - -/***************************************************************************** - * I2C - ****************************************************************************/ -void __init dove_i2c_init(void) -{ - orion_i2c_init(DOVE_I2C_PHYS_BASE, IRQ_DOVE_I2C, 10); -} - -/***************************************************************************** - * Time handling - ****************************************************************************/ -void __init dove_init_early(void) -{ - orion_time_set_base(TIMER_VIRT_BASE); - mvebu_mbus_init("marvell,dove-mbus", - BRIDGE_WINS_BASE, BRIDGE_WINS_SZ, - DOVE_MC_WINS_BASE, DOVE_MC_WINS_SZ); -} - -static int __init dove_find_tclk(void) -{ - return 166666667; -} - -void __init dove_timer_init(void) -{ - dove_tclk = dove_find_tclk(); - orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, - IRQ_DOVE_BRIDGE, dove_tclk); -} - -/***************************************************************************** - * XOR 0 - ****************************************************************************/ -static void __init dove_xor0_init(void) -{ - orion_xor0_init(DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE, - IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01); -} - -/***************************************************************************** - * XOR 1 - ****************************************************************************/ -static void __init dove_xor1_init(void) -{ - orion_xor1_init(DOVE_XOR1_PHYS_BASE, DOVE_XOR1_HIGH_PHYS_BASE, - IRQ_DOVE_XOR_10, IRQ_DOVE_XOR_11); -} - -/***************************************************************************** - * SDIO - ****************************************************************************/ -static u64 sdio_dmamask = DMA_BIT_MASK(32); - -static struct resource dove_sdio0_resources[] = { - { - .start = DOVE_SDIO0_PHYS_BASE, - .end = DOVE_SDIO0_PHYS_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_DOVE_SDIO0, - .end = IRQ_DOVE_SDIO0, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device dove_sdio0 = { - .name = "sdhci-dove", - .id = 0, - .dev = { - .dma_mask = &sdio_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .resource = dove_sdio0_resources, - .num_resources = ARRAY_SIZE(dove_sdio0_resources), -}; - -void __init dove_sdio0_init(void) -{ - platform_device_register(&dove_sdio0); -} - -static struct resource dove_sdio1_resources[] = { - { - .start = DOVE_SDIO1_PHYS_BASE, - .end = DOVE_SDIO1_PHYS_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_DOVE_SDIO1, - .end = IRQ_DOVE_SDIO1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device dove_sdio1 = { - .name = "sdhci-dove", - .id = 1, - .dev = { - .dma_mask = &sdio_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .resource = dove_sdio1_resources, - .num_resources = ARRAY_SIZE(dove_sdio1_resources), -}; - -void __init dove_sdio1_init(void) -{ - platform_device_register(&dove_sdio1); -} - -void __init dove_setup_cpu_wins(void) -{ - /* - * The PCIe windows will no longer be statically allocated - * here once Dove is migrated to the pci-mvebu driver. The - * non-PCIe windows will no longer be created here once Dove - * fully moves to DT. - */ - mvebu_mbus_add_window_remap_by_id(DOVE_MBUS_PCIE0_IO_TARGET, - DOVE_MBUS_PCIE0_IO_ATTR, - DOVE_PCIE0_IO_PHYS_BASE, - DOVE_PCIE0_IO_SIZE, - DOVE_PCIE0_IO_BUS_BASE); - mvebu_mbus_add_window_remap_by_id(DOVE_MBUS_PCIE1_IO_TARGET, - DOVE_MBUS_PCIE1_IO_ATTR, - DOVE_PCIE1_IO_PHYS_BASE, - DOVE_PCIE1_IO_SIZE, - DOVE_PCIE1_IO_BUS_BASE); - mvebu_mbus_add_window_by_id(DOVE_MBUS_PCIE0_MEM_TARGET, - DOVE_MBUS_PCIE0_MEM_ATTR, - DOVE_PCIE0_MEM_PHYS_BASE, - DOVE_PCIE0_MEM_SIZE); - mvebu_mbus_add_window_by_id(DOVE_MBUS_PCIE1_MEM_TARGET, - DOVE_MBUS_PCIE1_MEM_ATTR, - DOVE_PCIE1_MEM_PHYS_BASE, - DOVE_PCIE1_MEM_SIZE); - mvebu_mbus_add_window_by_id(DOVE_MBUS_CESA_TARGET, - DOVE_MBUS_CESA_ATTR, - DOVE_CESA_PHYS_BASE, - DOVE_CESA_SIZE); - mvebu_mbus_add_window_by_id(DOVE_MBUS_BOOTROM_TARGET, - DOVE_MBUS_BOOTROM_ATTR, - DOVE_BOOTROM_PHYS_BASE, - DOVE_BOOTROM_SIZE); - mvebu_mbus_add_window_by_id(DOVE_MBUS_SCRATCHPAD_TARGET, - DOVE_MBUS_SCRATCHPAD_ATTR, - DOVE_SCRATCHPAD_PHYS_BASE, - DOVE_SCRATCHPAD_SIZE); -} - -static struct resource orion_wdt_resource[] = { - DEFINE_RES_MEM(TIMER_PHYS_BASE, 0x04), - DEFINE_RES_MEM(RSTOUTn_MASK_PHYS, 0x04), -}; - -static struct platform_device orion_wdt_device = { - .name = "orion_wdt", - .id = -1, - .num_resources = ARRAY_SIZE(orion_wdt_resource), - .resource = orion_wdt_resource, -}; - -static void __init __maybe_unused orion_wdt_init(void) -{ - platform_device_register(&orion_wdt_device); -} - -static const struct dove_pmu_domain_initdata pmu_domains[] __initconst = { - { - .pwr_mask = PMU_PWR_VPU_PWR_DWN_MASK, - .rst_mask = PMU_SW_RST_VIDEO_MASK, - .iso_mask = PMU_ISO_VIDEO_MASK, - .name = "vpu-domain", - }, { - .pwr_mask = PMU_PWR_GPU_PWR_DWN_MASK, - .rst_mask = PMU_SW_RST_GPU_MASK, - .iso_mask = PMU_ISO_GPU_MASK, - .name = "gpu-domain", - }, { - /* sentinel */ - }, -}; - -static const struct dove_pmu_initdata pmu_data __initconst = { - .pmc_base = DOVE_PMU_VIRT_BASE, - .pmu_base = DOVE_PMU_VIRT_BASE + 0x8000, - .irq = IRQ_DOVE_PMU, - .irq_domain_start = IRQ_DOVE_PMU_START, - .domains = pmu_domains, -}; - -void __init dove_init(void) -{ - pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n", - (dove_tclk + 499999) / 1000000); - -#ifdef CONFIG_CACHE_TAUROS2 - tauros2_init(0); -#endif - dove_setup_cpu_wins(); - - /* Setup root of clk tree */ - dove_clk_init(); - - /* internal devices that every board has */ - dove_init_pmu_legacy(&pmu_data); - dove_rtc_init(); - dove_xor0_init(); - dove_xor1_init(); -} - -void dove_restart(enum reboot_mode mode, const char *cmd) -{ - /* - * Enable soft reset to assert RSTOUTn. - */ - writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK); - - /* - * Assert soft reset. - */ - writel(SOFT_RESET, SYSTEM_SOFT_RESET); - - while (1) - ; -} diff --git a/arch/arm/mach-dove/common.h b/arch/arm/mach-dove/common.h deleted file mode 100644 index 57ebc413d68c..000000000000 --- a/arch/arm/mach-dove/common.h +++ /dev/null @@ -1,46 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * arch/arm/mach-dove/common.h - * - * Core functions for Marvell Dove 88AP510 System On Chip - */ - -#ifndef __ARCH_DOVE_COMMON_H -#define __ARCH_DOVE_COMMON_H - -#include - -struct mv643xx_eth_platform_data; -struct mv_sata_platform_data; - -extern void dove_timer_init(void); - -/* - * Basic Dove init functions used early by machine-setup. - */ -void dove_map_io(void); -void dove_init(void); -void dove_init_early(void); -void dove_init_irq(void); -void dove_setup_cpu_wins(void); -void dove_ge00_init(struct mv643xx_eth_platform_data *eth_data); -void dove_sata_init(struct mv_sata_platform_data *sata_data); -#ifdef CONFIG_PCI -void dove_pcie_init(int init_port0, int init_port1); -#else -static inline void dove_pcie_init(int init_port0, int init_port1) { } -#endif -void dove_ehci0_init(void); -void dove_ehci1_init(void); -void dove_uart0_init(void); -void dove_uart1_init(void); -void dove_uart2_init(void); -void dove_uart3_init(void); -void dove_spi0_init(void); -void dove_spi1_init(void); -void dove_i2c_init(void); -void dove_sdio0_init(void); -void dove_sdio1_init(void); -void dove_restart(enum reboot_mode, const char *); - -#endif diff --git a/arch/arm/mach-dove/dove.h b/arch/arm/mach-dove/dove.h deleted file mode 100644 index e5054e3b0b78..000000000000 --- a/arch/arm/mach-dove/dove.h +++ /dev/null @@ -1,185 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* Generic definitions for Marvell Dove 88AP510 SoC */ - -#ifndef __ASM_ARCH_DOVE_H -#define __ASM_ARCH_DOVE_H - -#include "irqs.h" - -/* - * Marvell Dove address maps. - * - * phys virt size - * c8000000 fdb00000 1M Cryptographic SRAM - * e0000000 @runtime 128M PCIe-0 Memory space - * e8000000 @runtime 128M PCIe-1 Memory space - * f1000000 fec00000 1M on-chip south-bridge registers - * f1800000 fe400000 8M on-chip north-bridge registers - * f2000000 fee00000 1M PCIe-0 I/O space - * f2100000 fef00000 1M PCIe-1 I/O space - */ - -#define DOVE_CESA_PHYS_BASE 0xc8000000 -#define DOVE_CESA_VIRT_BASE IOMEM(0xfdb00000) -#define DOVE_CESA_SIZE SZ_1M - -#define DOVE_PCIE0_MEM_PHYS_BASE 0xe0000000 -#define DOVE_PCIE0_MEM_SIZE SZ_128M - -#define DOVE_PCIE1_MEM_PHYS_BASE 0xe8000000 -#define DOVE_PCIE1_MEM_SIZE SZ_128M - -#define DOVE_BOOTROM_PHYS_BASE 0xf8000000 -#define DOVE_BOOTROM_SIZE SZ_128M - -#define DOVE_SCRATCHPAD_PHYS_BASE 0xf0000000 -#define DOVE_SCRATCHPAD_VIRT_BASE IOMEM(0xfdd00000) -#define DOVE_SCRATCHPAD_SIZE SZ_1M - -#define DOVE_SB_REGS_PHYS_BASE 0xf1000000 -#define DOVE_SB_REGS_VIRT_BASE IOMEM(0xfec00000) -#define DOVE_SB_REGS_SIZE SZ_1M - -#define DOVE_NB_REGS_PHYS_BASE 0xf1800000 -#define DOVE_NB_REGS_VIRT_BASE IOMEM(0xfe400000) -#define DOVE_NB_REGS_SIZE SZ_8M - -#define DOVE_PCIE0_IO_PHYS_BASE 0xf2000000 -#define DOVE_PCIE0_IO_BUS_BASE 0x00000000 -#define DOVE_PCIE0_IO_SIZE SZ_64K - -#define DOVE_PCIE1_IO_PHYS_BASE 0xf2100000 -#define DOVE_PCIE1_IO_BUS_BASE 0x00010000 -#define DOVE_PCIE1_IO_SIZE SZ_64K - -/* - * Dove Core Registers Map - */ - -/* SPI, I2C, UART */ -#define DOVE_I2C_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x11000) -#define DOVE_UART0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12000) -#define DOVE_UART0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12000) -#define DOVE_UART1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12100) -#define DOVE_UART1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12100) -#define DOVE_UART2_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12200) -#define DOVE_UART2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12200) -#define DOVE_UART3_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12300) -#define DOVE_UART3_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12300) -#define DOVE_SPI0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x10600) -#define DOVE_SPI1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x14600) - -/* North-South Bridge */ -#define BRIDGE_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x20000) -#define BRIDGE_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x20000) -#define BRIDGE_WINS_BASE (BRIDGE_PHYS_BASE) -#define BRIDGE_WINS_SZ (0x80) - -/* Cryptographic Engine */ -#define DOVE_CRYPT_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x30000) - -/* PCIe 0 */ -#define DOVE_PCIE0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x40000) - -/* USB */ -#define DOVE_USB0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x50000) -#define DOVE_USB1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x51000) - -/* XOR 0 Engine */ -#define DOVE_XOR0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60800) -#define DOVE_XOR0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60800) -#define DOVE_XOR0_HIGH_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60A00) -#define DOVE_XOR0_HIGH_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60A00) - -/* XOR 1 Engine */ -#define DOVE_XOR1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60900) -#define DOVE_XOR1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60900) -#define DOVE_XOR1_HIGH_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60B00) -#define DOVE_XOR1_HIGH_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60B00) - -/* Gigabit Ethernet */ -#define DOVE_GE00_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x70000) - -/* PCIe 1 */ -#define DOVE_PCIE1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x80000) - -/* CAFE */ -#define DOVE_SDIO0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x92000) -#define DOVE_SDIO1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x90000) -#define DOVE_CAM_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x94000) -#define DOVE_CAFE_WIN_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x98000) - -/* SATA */ -#define DOVE_SATA_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xa0000) - -/* I2S/SPDIF */ -#define DOVE_AUD0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xb0000) -#define DOVE_AUD1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xb4000) - -/* NAND Flash Controller */ -#define DOVE_NFC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xc0000) - -/* MPP, GPIO, Reset Sampling */ -#define DOVE_MPP_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0200) -#define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10) -#define DOVE_RESET_SAMPLE_LO (DOVE_MPP_VIRT_BASE + 0x014) -#define DOVE_RESET_SAMPLE_HI (DOVE_MPP_VIRT_BASE + 0x018) -#define DOVE_GPIO_LO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0400) -#define DOVE_GPIO_HI_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0420) -#define DOVE_GPIO2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe8400) -#define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe803c) -#define DOVE_AU1_SPDIFO_GPIO_EN (1 << 1) -#define DOVE_NAND_GPIO_EN (1 << 0) -#define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_LO_VIRT_BASE + 0x40) -#define DOVE_SPI_GPIO_SEL (1 << 5) -#define DOVE_UART1_GPIO_SEL (1 << 4) -#define DOVE_AU1_GPIO_SEL (1 << 3) -#define DOVE_CAM_GPIO_SEL (1 << 2) -#define DOVE_SD1_GPIO_SEL (1 << 1) -#define DOVE_SD0_GPIO_SEL (1 << 0) - -/* Power Management */ -#define DOVE_PMU_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0000) -#define DOVE_PMU_SIG_CTRL (DOVE_PMU_VIRT_BASE + 0x802c) - -/* Real Time Clock */ -#define DOVE_RTC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xd8500) - -/* AC97 */ -#define DOVE_AC97_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xe0000) -#define DOVE_AC97_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe0000) - -/* Peripheral DMA */ -#define DOVE_PDMA_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xe4000) -#define DOVE_PDMA_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe4000) - -#define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE + 0xe802C) -#define DOVE_TWSI_ENABLE_OPTION1 (1 << 7) -#define DOVE_GLOBAL_CONFIG_2 (DOVE_SB_REGS_VIRT_BASE + 0xe8030) -#define DOVE_TWSI_ENABLE_OPTION2 (1 << 20) -#define DOVE_TWSI_ENABLE_OPTION3 (1 << 21) -#define DOVE_TWSI_OPTION3_GPIO (1 << 22) -#define DOVE_SSP_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xec000) -#define DOVE_SSP_CTRL_STATUS_1 (DOVE_SB_REGS_VIRT_BASE + 0xe8034) -#define DOVE_SSP_ON_AU1 (1 << 0) -#define DOVE_SSP_CLOCK_ENABLE (1 << 1) -#define DOVE_SSP_BPB_CLOCK_SRC_SSP (1 << 11) -/* Memory Controller */ -#define DOVE_MC_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x00000) -#define DOVE_MC_WINS_BASE (DOVE_MC_PHYS_BASE + 0x100) -#define DOVE_MC_WINS_SZ (0x8) -#define DOVE_MC_VIRT_BASE (DOVE_NB_REGS_VIRT_BASE + 0x00000) - -/* LCD Controller */ -#define DOVE_LCD_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x10000) -#define DOVE_LCD1_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x20000) -#define DOVE_LCD2_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x10000) -#define DOVE_LCD_DCON_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x30000) - -/* Graphic Engine */ -#define DOVE_GPU_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x40000) - -/* Video Engine */ -#define DOVE_VPU_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x400000) - -#endif diff --git a/arch/arm/mach-dove/irq.c b/arch/arm/mach-dove/irq.c deleted file mode 100644 index 027a8f87bc2e..000000000000 --- a/arch/arm/mach-dove/irq.c +++ /dev/null @@ -1,81 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * arch/arm/mach-dove/irq.c - * - * Dove IRQ handling. - */ -#include -#include -#include -#include - -#include -#include - -#include "pm.h" -#include "bridge-regs.h" -#include "common.h" - -static int __initdata gpio0_irqs[4] = { - IRQ_DOVE_GPIO_0_7, - IRQ_DOVE_GPIO_8_15, - IRQ_DOVE_GPIO_16_23, - IRQ_DOVE_GPIO_24_31, -}; - -static int __initdata gpio1_irqs[4] = { - IRQ_DOVE_HIGH_GPIO, - 0, - 0, - 0, -}; - -static int __initdata gpio2_irqs[4] = { - 0, - 0, - 0, - 0, -}; - -static void __iomem *dove_irq_base = IRQ_VIRT_BASE; - -static asmlinkage void -__exception_irq_entry dove_legacy_handle_irq(struct pt_regs *regs) -{ - u32 stat; - - stat = readl_relaxed(dove_irq_base + IRQ_CAUSE_LOW_OFF); - stat &= readl_relaxed(dove_irq_base + IRQ_MASK_LOW_OFF); - if (stat) { - unsigned int hwirq = 1 + __fls(stat); - handle_IRQ(hwirq, regs); - return; - } - stat = readl_relaxed(dove_irq_base + IRQ_CAUSE_HIGH_OFF); - stat &= readl_relaxed(dove_irq_base + IRQ_MASK_HIGH_OFF); - if (stat) { - unsigned int hwirq = 33 + __fls(stat); - handle_IRQ(hwirq, regs); - return; - } -} - -void __init dove_init_irq(void) -{ - orion_irq_init(1, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF); - orion_irq_init(33, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF); - - set_handle_irq(dove_legacy_handle_irq); - - /* - * Initialize gpiolib for GPIOs 0-71. - */ - orion_gpio_init(0, 32, DOVE_GPIO_LO_VIRT_BASE, 0, - IRQ_DOVE_GPIO_START, gpio0_irqs); - - orion_gpio_init(32, 32, DOVE_GPIO_HI_VIRT_BASE, 0, - IRQ_DOVE_GPIO_START + 32, gpio1_irqs); - - orion_gpio_init(64, 8, DOVE_GPIO2_VIRT_BASE, 0, - IRQ_DOVE_GPIO_START + 64, gpio2_irqs); -} diff --git a/arch/arm/mach-dove/irqs.h b/arch/arm/mach-dove/irqs.h deleted file mode 100644 index 5467098c7042..000000000000 --- a/arch/arm/mach-dove/irqs.h +++ /dev/null @@ -1,89 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* IRQ definitions for Marvell Dove 88AP510 SoC */ - -#ifndef __ASM_ARCH_IRQS_H -#define __ASM_ARCH_IRQS_H - -/* - * Dove Low Interrupt Controller - */ -#define IRQ_DOVE_BRIDGE (1 + 0) -#define IRQ_DOVE_H2C (1 + 1) -#define IRQ_DOVE_C2H (1 + 2) -#define IRQ_DOVE_NAND (1 + 3) -#define IRQ_DOVE_PDMA (1 + 4) -#define IRQ_DOVE_SPI1 (1 + 5) -#define IRQ_DOVE_SPI0 (1 + 6) -#define IRQ_DOVE_UART_0 (1 + 7) -#define IRQ_DOVE_UART_1 (1 + 8) -#define IRQ_DOVE_UART_2 (1 + 9) -#define IRQ_DOVE_UART_3 (1 + 10) -#define IRQ_DOVE_I2C (1 + 11) -#define IRQ_DOVE_GPIO_0_7 (1 + 12) -#define IRQ_DOVE_GPIO_8_15 (1 + 13) -#define IRQ_DOVE_GPIO_16_23 (1 + 14) -#define IRQ_DOVE_PCIE0_ERR (1 + 15) -#define IRQ_DOVE_PCIE0 (1 + 16) -#define IRQ_DOVE_PCIE1_ERR (1 + 17) -#define IRQ_DOVE_PCIE1 (1 + 18) -#define IRQ_DOVE_I2S0 (1 + 19) -#define IRQ_DOVE_I2S0_ERR (1 + 20) -#define IRQ_DOVE_I2S1 (1 + 21) -#define IRQ_DOVE_I2S1_ERR (1 + 22) -#define IRQ_DOVE_USB_ERR (1 + 23) -#define IRQ_DOVE_USB0 (1 + 24) -#define IRQ_DOVE_USB1 (1 + 25) -#define IRQ_DOVE_GE00_RX (1 + 26) -#define IRQ_DOVE_GE00_TX (1 + 27) -#define IRQ_DOVE_GE00_MISC (1 + 28) -#define IRQ_DOVE_GE00_SUM (1 + 29) -#define IRQ_DOVE_GE00_ERR (1 + 30) -#define IRQ_DOVE_CRYPTO (1 + 31) - -/* - * Dove High Interrupt Controller - */ -#define IRQ_DOVE_AC97 (1 + 32) -#define IRQ_DOVE_PMU (1 + 33) -#define IRQ_DOVE_CAM (1 + 34) -#define IRQ_DOVE_SDIO0 (1 + 35) -#define IRQ_DOVE_SDIO1 (1 + 36) -#define IRQ_DOVE_SDIO0_WAKEUP (1 + 37) -#define IRQ_DOVE_SDIO1_WAKEUP (1 + 38) -#define IRQ_DOVE_XOR_00 (1 + 39) -#define IRQ_DOVE_XOR_01 (1 + 40) -#define IRQ_DOVE_XOR0_ERR (1 + 41) -#define IRQ_DOVE_XOR_10 (1 + 42) -#define IRQ_DOVE_XOR_11 (1 + 43) -#define IRQ_DOVE_XOR1_ERR (1 + 44) -#define IRQ_DOVE_LCD_DCON (1 + 45) -#define IRQ_DOVE_LCD1 (1 + 46) -#define IRQ_DOVE_LCD0 (1 + 47) -#define IRQ_DOVE_GPU (1 + 48) -#define IRQ_DOVE_PERFORM_MNTR (1 + 49) -#define IRQ_DOVE_VPRO_DMA1 (1 + 51) -#define IRQ_DOVE_SSP_TIMER (1 + 54) -#define IRQ_DOVE_SSP (1 + 55) -#define IRQ_DOVE_MC_L2_ERR (1 + 56) -#define IRQ_DOVE_CRYPTO_ERR (1 + 59) -#define IRQ_DOVE_GPIO_24_31 (1 + 60) -#define IRQ_DOVE_HIGH_GPIO (1 + 61) -#define IRQ_DOVE_SATA (1 + 62) - -/* - * DOVE General Purpose Pins - */ -#define IRQ_DOVE_GPIO_START 65 -#define NR_GPIO_IRQS 64 - -/* - * PMU interrupts - */ -#define IRQ_DOVE_PMU_START (IRQ_DOVE_GPIO_START + NR_GPIO_IRQS) -#define NR_PMU_IRQS 7 -#define IRQ_DOVE_RTC (IRQ_DOVE_PMU_START + 5) - -#define DOVE_NR_IRQS (IRQ_DOVE_PMU_START + NR_PMU_IRQS) - - -#endif diff --git a/arch/arm/mach-dove/mpp.c b/arch/arm/mach-dove/mpp.c deleted file mode 100644 index e41bd473abe9..000000000000 --- a/arch/arm/mach-dove/mpp.c +++ /dev/null @@ -1,159 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * arch/arm/mach-dove/mpp.c - * - * MPP functions for Marvell Dove SoCs - */ - -#include -#include -#include -#include -#include -#include "dove.h" -#include "mpp.h" - -struct dove_mpp_grp { - int start; - int end; -}; - -/* Map a group to a range of GPIO pins in that group */ -static const struct dove_mpp_grp dove_mpp_grp[] = { - [MPP_24_39] = { - .start = 24, - .end = 39, - }, - [MPP_40_45] = { - .start = 40, - .end = 45, - }, - [MPP_46_51] = { - .start = 46, - .end = 51, - }, - [MPP_58_61] = { - .start = 58, - .end = 61, - }, - [MPP_62_63] = { - .start = 62, - .end = 63, - }, -}; - -/* Enable gpio for a range of pins. mode should be a combination of - GPIO_OUTPUT_OK | GPIO_INPUT_OK */ -static void __init dove_mpp_gpio_mode(int start, int end, int gpio_mode) -{ - int i; - - for (i = start; i <= end; i++) - orion_gpio_set_valid(i, gpio_mode); -} - -/* Dump all the extra MPP registers. The platform code will dump the - registers for pins 0-23. */ -static void __init dove_mpp_dump_regs(void) -{ - pr_debug("PMU_CTRL4_CTRL: %08x\n", - readl(DOVE_MPP_CTRL4_VIRT_BASE)); - - pr_debug("PMU_MPP_GENERAL_CTRL: %08x\n", - readl(DOVE_PMU_MPP_GENERAL_CTRL)); - - pr_debug("MPP_GENERAL: %08x\n", readl(DOVE_MPP_GENERAL_VIRT_BASE)); -} - -static void __init dove_mpp_cfg_nfc(int sel) -{ - u32 mpp_gen_cfg = readl(DOVE_MPP_GENERAL_VIRT_BASE); - - mpp_gen_cfg &= ~0x1; - mpp_gen_cfg |= sel; - writel(mpp_gen_cfg, DOVE_MPP_GENERAL_VIRT_BASE); - - dove_mpp_gpio_mode(64, 71, GPIO_OUTPUT_OK); -} - -static void __init dove_mpp_cfg_au1(int sel) -{ - u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); - u32 ssp_ctrl1 = readl(DOVE_SSP_CTRL_STATUS_1); - u32 mpp_gen_ctrl = readl(DOVE_MPP_GENERAL_VIRT_BASE); - u32 global_cfg_2 = readl(DOVE_GLOBAL_CONFIG_2); - - mpp_ctrl4 &= ~(DOVE_AU1_GPIO_SEL); - ssp_ctrl1 &= ~(DOVE_SSP_ON_AU1); - mpp_gen_ctrl &= ~(DOVE_AU1_SPDIFO_GPIO_EN); - global_cfg_2 &= ~(DOVE_TWSI_OPTION3_GPIO); - - if (!sel || sel == 0x2) - dove_mpp_gpio_mode(52, 57, 0); - else - dove_mpp_gpio_mode(52, 57, GPIO_OUTPUT_OK | GPIO_INPUT_OK); - - if (sel & 0x1) { - global_cfg_2 |= DOVE_TWSI_OPTION3_GPIO; - dove_mpp_gpio_mode(56, 57, 0); - } - if (sel & 0x2) { - mpp_gen_ctrl |= DOVE_AU1_SPDIFO_GPIO_EN; - dove_mpp_gpio_mode(57, 57, GPIO_OUTPUT_OK | GPIO_INPUT_OK); - } - if (sel & 0x4) { - ssp_ctrl1 |= DOVE_SSP_ON_AU1; - dove_mpp_gpio_mode(52, 55, 0); - } - if (sel & 0x8) - mpp_ctrl4 |= DOVE_AU1_GPIO_SEL; - - writel(mpp_ctrl4, DOVE_MPP_CTRL4_VIRT_BASE); - writel(ssp_ctrl1, DOVE_SSP_CTRL_STATUS_1); - writel(mpp_gen_ctrl, DOVE_MPP_GENERAL_VIRT_BASE); - writel(global_cfg_2, DOVE_GLOBAL_CONFIG_2); -} - -/* Configure the group registers, enabling GPIO if sel indicates the - pin is to be used for GPIO */ -static void __init dove_mpp_conf_grp(unsigned int *mpp_grp_list) -{ - u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); - int gpio_mode; - - for ( ; *mpp_grp_list; mpp_grp_list++) { - unsigned int num = MPP_NUM(*mpp_grp_list); - unsigned int sel = MPP_SEL(*mpp_grp_list); - - if (num > MPP_GRP_MAX) { - pr_err("dove: invalid MPP GRP number (%u)\n", num); - continue; - } - - mpp_ctrl4 &= ~(0x1 << num); - mpp_ctrl4 |= sel << num; - - gpio_mode = sel ? GPIO_OUTPUT_OK | GPIO_INPUT_OK : 0; - dove_mpp_gpio_mode(dove_mpp_grp[num].start, - dove_mpp_grp[num].end, gpio_mode); - } - writel(mpp_ctrl4, DOVE_MPP_CTRL4_VIRT_BASE); -} - -/* Configure the various MPP pins on Dove */ -void __init dove_mpp_conf(unsigned int *mpp_list, - unsigned int *mpp_grp_list, - unsigned int grp_au1_52_57, - unsigned int grp_nfc_64_71) -{ - dove_mpp_dump_regs(); - - /* Use platform code for pins 0-23 */ - orion_mpp_conf(mpp_list, 0, MPP_MAX, DOVE_MPP_VIRT_BASE); - - dove_mpp_conf_grp(mpp_grp_list); - dove_mpp_cfg_au1(grp_au1_52_57); - dove_mpp_cfg_nfc(grp_nfc_64_71); - - dove_mpp_dump_regs(); -} diff --git a/arch/arm/mach-dove/mpp.h b/arch/arm/mach-dove/mpp.h deleted file mode 100644 index 2e4b89c86ca8..000000000000 --- a/arch/arm/mach-dove/mpp.h +++ /dev/null @@ -1,197 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ARCH_DOVE_MPP_CODED_H -#define __ARCH_DOVE_MPP_CODED_H - -#define MPP(_num, _sel, _in, _out) ( \ - /* MPP number */ ((_num) & 0xff) | \ - /* MPP select value */ (((_sel) & 0xf) << 8) | \ - /* may be input signal */ ((!!(_in)) << 12) | \ - /* may be output signal */ ((!!(_out)) << 13)) - -#define MPP0_GPIO0 MPP(0, 0x0, 1, 1) -#define MPP0_UA2_RTSn MPP(0, 0x2, 0, 0) -#define MPP0_SDIO0_CD MPP(0, 0x3, 0, 0) -#define MPP0_LCD0_PWM MPP(0, 0xf, 0, 0) - -#define MPP1_GPIO1 MPP(1, 0x0, 1, 1) -#define MPP1_UA2_CTSn MPP(1, 0x2, 0, 0) -#define MPP1_SDIO0_WP MPP(1, 0x3, 0, 0) -#define MPP1_LCD1_PWM MPP(1, 0xf, 0, 0) - -#define MPP2_GPIO2 MPP(2, 0x0, 1, 1) -#define MPP2_SATA_PRESENT MPP(2, 0x1, 0, 0) -#define MPP2_UA2_TXD MPP(2, 0x2, 0, 0) -#define MPP2_SDIO0_BUS_POWER MPP(2, 0x3, 0, 0) -#define MPP2_UA_RTSn1 MPP(2, 0x4, 0, 0) - -#define MPP3_GPIO3 MPP(3, 0x0, 1, 1) -#define MPP3_SATA_ACT MPP(3, 0x1, 0, 0) -#define MPP3_UA2_RXD MPP(3, 0x2, 0, 0) -#define MPP3_SDIO0_LED_CTRL MPP(3, 0x3, 0, 0) -#define MPP3_UA_CTSn1 MPP(3, 0x4, 0, 0) -#define MPP3_SPI_LCD_CS1 MPP(3, 0xf, 0, 0) - -#define MPP4_GPIO4 MPP(4, 0x0, 1, 1) -#define MPP4_UA3_RTSn MPP(4, 0x2, 0, 0) -#define MPP4_SDIO1_CD MPP(4, 0x3, 0, 0) -#define MPP4_SPI_1_MISO MPP(4, 0x4, 0, 0) - -#define MPP5_GPIO5 MPP(5, 0x0, 1, 1) -#define MPP5_UA3_CTSn MPP(5, 0x2, 0, 0) -#define MPP5_SDIO1_WP MPP(5, 0x3, 0, 0) -#define MPP5_SPI_1_CS MPP(5, 0x4, 0, 0) - -#define MPP6_GPIO6 MPP(6, 0x0, 1, 1) -#define MPP6_UA3_TXD MPP(6, 0x2, 0, 0) -#define MPP6_SDIO1_BUS_POWER MPP(6, 0x3, 0, 0) -#define MPP6_SPI_1_MOSI MPP(6, 0x4, 0, 0) - -#define MPP7_GPIO7 MPP(7, 0x0, 1, 1) -#define MPP7_UA3_RXD MPP(7, 0x2, 0, 0) -#define MPP7_SDIO1_LED_CTRL MPP(7, 0x3, 0, 0) -#define MPP7_SPI_1_SCK MPP(7, 0x4, 0, 0) - -#define MPP8_GPIO8 MPP(8, 0x0, 1, 1) -#define MPP8_WD_RST_OUT MPP(8, 0x1, 0, 0) - -#define MPP9_GPIO9 MPP(9, 0x0, 1, 1) -#define MPP9_PEX1_CLKREQn MPP(9, 0x5, 0, 0) - -#define MPP10_GPIO10 MPP(10, 0x0, 1, 1) -#define MPP10_SSP_SCLK MPP(10, 0x5, 0, 0) - -#define MPP11_GPIO11 MPP(11, 0x0, 1, 1) -#define MPP11_SATA_PRESENT MPP(11, 0x1, 0, 0) -#define MPP11_SATA_ACT MPP(11, 0x2, 0, 0) -#define MPP11_SDIO0_LED_CTRL MPP(11, 0x3, 0, 0) -#define MPP11_SDIO1_LED_CTRL MPP(11, 0x4, 0, 0) -#define MPP11_PEX0_CLKREQn MPP(11, 0x5, 0, 0) - -#define MPP12_GPIO12 MPP(12, 0x0, 1, 1) -#define MPP12_SATA_ACT MPP(12, 0x1, 0, 0) -#define MPP12_UA2_RTSn MPP(12, 0x2, 0, 0) -#define MPP12_AD0_I2S_EXT_MCLK MPP(12, 0x3, 0, 0) -#define MPP12_SDIO1_CD MPP(12, 0x4, 0, 0) - -#define MPP13_GPIO13 MPP(13, 0x0, 1, 1) -#define MPP13_UA2_CTSn MPP(13, 0x2, 0, 0) -#define MPP13_AD1_I2S_EXT_MCLK MPP(13, 0x3, 0, 0) -#define MPP13_SDIO1WP MPP(13, 0x4, 0, 0) -#define MPP13_SSP_EXTCLK MPP(13, 0x5, 0, 0) - -#define MPP14_GPIO14 MPP(14, 0x0, 1, 1) -#define MPP14_UA2_TXD MPP(14, 0x2, 0, 0) -#define MPP14_SDIO1_BUS_POWER MPP(14, 0x4, 0, 0) -#define MPP14_SSP_RXD MPP(14, 0x5, 0, 0) - -#define MPP15_GPIO15 MPP(15, 0x0, 1, 1) -#define MPP15_UA2_RXD MPP(15, 0x2, 0, 0) -#define MPP15_SDIO1_LED_CTRL MPP(15, 0x4, 0, 0) -#define MPP15_SSP_SFRM MPP(15, 0x5, 0, 0) - -#define MPP16_GPIO16 MPP(16, 0x0, 1, 1) -#define MPP16_UA3_RTSn MPP(16, 0x2, 0, 0) -#define MPP16_SDIO0_CD MPP(16, 0x3, 0, 0) -#define MPP16_SPI_LCD_CS1 MPP(16, 0x4, 0, 0) -#define MPP16_AC97_SDATA_IN1 MPP(16, 0x5, 0, 0) - -#define MPP17_GPIO17 MPP(17, 0x0, 1, 1) -#define MPP17_AC97_SYSCLK_OUT MPP(17, 0x1, 0, 0) -#define MPP17_UA3_CTSn MPP(17, 0x2, 0, 0) -#define MPP17_SDIO0_WP MPP(17, 0x3, 0, 0) -#define MPP17_TW_SDA2 MPP(17, 0x4, 0, 0) -#define MPP17_AC97_SDATA_IN2 MPP(17, 0x5, 0, 0) - -#define MPP18_GPIO18 MPP(18, 0x0, 1, 1) -#define MPP18_UA3_TXD MPP(18, 0x2, 0, 0) -#define MPP18_SDIO0_BUS_POWER MPP(18, 0x3, 0, 0) -#define MPP18_LCD0_PWM MPP(18, 0x4, 0, 0) -#define MPP18_AC_SDATA_IN3 MPP(18, 0x5, 0, 0) - -#define MPP19_GPIO19 MPP(19, 0x0, 1, 1) -#define MPP19_UA3_RXD MPP(19, 0x2, 0, 0) -#define MPP19_SDIO0_LED_CTRL MPP(19, 0x3, 0, 0) -#define MPP19_TW_SCK2 MPP(19, 0x4, 0, 0) - -#define MPP20_GPIO20 MPP(20, 0x0, 1, 1) -#define MPP20_AC97_SYSCLK_OUT MPP(20, 0x1, 0, 0) -#define MPP20_SPI_LCD_MISO MPP(20, 0x2, 0, 0) -#define MPP20_SDIO1_CD MPP(20, 0x3, 0, 0) -#define MPP20_SDIO0_CD MPP(20, 0x5, 0, 0) -#define MPP20_SPI_1_MISO MPP(20, 0x6, 0, 0) - -#define MPP21_GPIO21 MPP(21, 0x0, 1, 1) -#define MPP21_UA1_RTSn MPP(21, 0x1, 0, 0) -#define MPP21_SPI_LCD_CS0 MPP(21, 0x2, 0, 0) -#define MPP21_SDIO1_WP MPP(21, 0x3, 0, 0) -#define MPP21_SSP_SFRM MPP(21, 0x4, 0, 0) -#define MPP21_SDIO0_WP MPP(21, 0x5, 0, 0) -#define MPP21_SPI_1_CS MPP(21, 0x6, 0, 0) - -#define MPP22_GPIO22 MPP(22, 0x0, 1, 1) -#define MPP22_UA1_CTSn MPP(22, 0x1, 0, 0) -#define MPP22_SPI_LCD_MOSI MPP(22, 0x2, 0, 0) -#define MPP22_SDIO1_BUS_POWER MPP(22, 0x3, 0, 0) -#define MPP22_SSP_TXD MPP(22, 0x4, 0, 0) -#define MPP22_SDIO0_BUS_POWER MPP(22, 0x5, 0, 0) -#define MPP22_SPI_1_MOSI MPP(22, 0x6, 0, 0) - -#define MPP23_GPIO23 MPP(23, 0x0, 1, 1) -#define MPP23_SPI_LCD_SCK MPP(23, 0x2, 0, 0) -#define MPP23_SDIO1_LED_CTRL MPP(23, 0x3, 0, 0) -#define MPP23_SSP_SCLK MPP(23, 0x4, 0, 0) -#define MPP23_SDIO0_LED_CTRL MPP(23, 0x5, 0, 0) -#define MPP23_SPI_1_SCK MPP(23, 0x6, 0, 0) - -#define MPP_MAX 23 - -#define MPP_GRP(_grp, _mode) MPP((_grp), (_mode), 0, 0) - -/* for MPP groups _num is a group index */ -enum dove_mpp_grp_idx { - MPP_24_39 = 2, - MPP_40_45 = 0, - MPP_46_51 = 1, - MPP_58_61 = 5, - MPP_62_63 = 4, - MPP_GRP_MAX = 5, -}; - -#define MPP_GRP_24_39_GPIO MPP_GRP(MPP_24_39, 0x1) -#define MPP_GRP_24_39_CAM MPP_GRP(MPP_24_39, 0x0) - -#define MPP_GRP_40_45_GPIO MPP_GRP(MPP_40_45, 0x1) -#define MPP_GRP_40_45_SD0 MPP_GRP(MPP_40_45, 0x0) - -#define MPP_GRP_46_51_GPIO MPP_GRP(MPP_46_51, 0x1) -#define MPP_GRP_46_51_SD1 MPP_GRP(MPP_46_51, 0x0) - -#define MPP_GRP_58_61_GPIO MPP_GRP(MPP_58_61, 0x1) -#define MPP_GRP_58_61_SPI MPP_GRP(MPP_58_61, 0x0) - -#define MPP_GRP_62_63_GPIO MPP_GRP(MPP_62_63, 0x1) -#define MPP_GRP_62_63_UA1 MPP_GRP(MPP_62_63, 0x0) - -/* The MPP[64:71] control differs from other groups */ -#define MPP_GRP_NFC_64_71_GPO 0x1 -#define MPP_GRP_NFC_64_71_NFC 0x0 - -/* - * The MPP[52:57] functionality is encoded by 4 bits in different - * registers. The _num field in this case encodes those bits in - * correspodence with Table 135 of 88AP510 Functional specification - */ -#define MPP_GRP_AU1_52_57_AU1 0x0 -#define MPP_GRP_AU1_52_57_AU1_GPIO57 0x2 -#define MPP_GRP_AU1_52_57_GPIO 0xa -#define MPP_GRP_AU1_52_57_TW_GPIO 0xb -#define MPP_GRP_AU1_52_57_AU1_SSP 0xc -#define MPP_GRP_AU1_52_57_SSP_GPIO 0xe -#define MPP_GRP_AU1_52_57_SSP_TW 0xf - -void dove_mpp_conf(unsigned int *mpp_list, - unsigned int *mpp_grp_list, - unsigned int grp_au1_52_57, - unsigned int grp_nfc_64_71); - -#endif /* __ARCH_DOVE_MPP_CODED_H */ diff --git a/arch/arm/mach-dove/pcie.c b/arch/arm/mach-dove/pcie.c deleted file mode 100644 index 3044b7e03890..000000000000 --- a/arch/arm/mach-dove/pcie.c +++ /dev/null @@ -1,226 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * arch/arm/mach-dove/pcie.c - * - * PCIe functions for Marvell Dove 88AP510 SoC - */ - -#include -#include -#include -#include