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Date: Tue, 8 Sep 2026 17:43:22 -0700
From: Jakub Kicinski <kuba@kernel.org>
To: Maxime Chevallier <maxime.chevallier@bootlin.com>
Cc: "Jan Havran (Advantech Czech)" <havran.jan@email.cz>, Hauke Mehrtens
 <hauke@hauke-m.de>, Andrew Lunn <andrew@lunn.ch>, Vladimir Oltean
 <olteanv@gmail.com>, Paolo Abeni <pabeni@redhat.com>, Eric Dumazet
 <edumazet@google.com>, "David S. Miller" <davem@davemloft.net>, Daniel
 Golle <daniel@makrotopia.org>, netdev@vger.kernel.org,
 linux-kernel@vger.kernel.org
Subject: Re: [PATCH net 3/3] net: dsa: lantiq_gswip: fix
 GSWIP_MDIO_PHY_FCONTX_EN value
Message-ID: <20260908174322.61223934@kernel.org>
In-Reply-To: <b7d56704-2aed-464f-8295-2ad70e4afa2c@bootlin.com>
References: <20260907134818.16670-1-havran.jan@email.cz>
	<20260907134818.16670-4-havran.jan@email.cz>
	<b7d56704-2aed-464f-8295-2ad70e4afa2c@bootlin.com>
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On Mon, 7 Sep 2026 18:28:32 +0200 Maxime Chevallier wrote:
> On 9/7/26 15:48, Jan Havran (Advantech Czech) wrote:
> > Per the GSW145 data sheet, the FCONTX (bits 8:7) and FCONRX (bits 6:5)
> > flow-control fields of the PHY_ADDR_n register both encode 00 = AUTO,
> > 01 = EN, 10 = reserved, 11 = DIS. GSWIP_MDIO_PHY_FCONTX_EN was 0x0100,
> > i.e. field value 10 (the reserved encoding), instead of 0x0080 (01 = EN);
> > FCONRX_EN is already 0x0020 (01). Enabling tx flow control therefore wrote
> > the reserved value.
> > 
> > Set FCONTX_EN to 0x0080. The register is shared by all supported parts.
> > 
> > Fixes: 14fceff4771e ("net: dsa: Add Lantiq / Intel DSA driver for vrx200")
> > Signed-off-by: Jan Havran (Advantech Czech) <havran.jan@email.cz>  
> 
> Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com>

Other than this last patch the series reads like net-next material 
to me TBH. New board enablement. Is that fair?

No need to repost either way.

And thanks for quick reviews!