From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 72AA62472A6 for ; Wed, 9 Sep 2026 00:13:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788912785; cv=none; b=sKQ2XWTcHOPqsodkWsnv/baQxi1WWcNHilcTPiKk1Y4kMcmkGTNQBKOKMv4aAMKtb1A5OTzW0BqH0BRiQ3EjuvRhgyrVImACJBBLXI2yHN89TLXln9cDeMjKUlqvOiPmTLdC3ErQaX+tnDRn5e2tmKZeI7r/R4B+XsYHgedusCk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788912785; c=relaxed/simple; bh=xNviF0x+9Ezvq2RBwqqfdR68vwj/iGmWyIWY9YebzMc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=GerdV2eRaV3WpoHZ1ER3WC01Io2QxHMVtBnXHxyVNBYVixx8r8l0Bcwgy+3c+OYhCmvTU7QTLV2y+Le4zZIaC2281g0sQBH+OVXNx8ET8LryoLML5yt3xCmTJEuZmTWqw6BMpwJcyhRuaeW2SIUislRnzWL2Doa2Lvc1/6+h7TY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=h7lQTFh3; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="h7lQTFh3" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 787D41F00A3A; Wed, 9 Sep 2026 00:13:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788912784; bh=gPSXCb0eA8BM+P5Y//s4nfh/kZxqoCvqmOhim53CK5s=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=h7lQTFh3CQAnVksW6Zj8yeFGo7my2tdk7q88OzLB8reV60Tf8cIBQ8aUNQ7l99QNT MPe2KsZ/cFiQ0C2uhIXNbURCHGedprS/4JIJiL5PiIGtG7agSfZzQl2hRqwxSMFARY xAwGRRUXO0PFZBO9UXLBtUHRCbGOV2ipPJhU64XfG0ivy1Z9nDBV9haDNHi+I9qtCK yPuyGvFZTXn2EUkPEU/7k27XL89HUMsVmZ8YOVGGml2AEo1o6yQspIObhbnmHJ+Qe1 Z60cPKiHh9X8s4WmghurVMSk5cHVkd4bRaewavpIB7Eq2bSVI2OJPOgUtpjTSozifJ H05AuE7fHa1HA== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Nam Cao Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 2/3] riscv: word-at-a-time: improve find_zero() without Zbb Date: Wed, 9 Sep 2026 07:53:11 +0800 Message-ID: <20260908235312.8440-3-jszhang@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260908235312.8440-1-jszhang@kernel.org> References: <20260908235312.8440-1-jszhang@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Previous commit improved the find_zero() performance for !RISCV_ISA_ZBB. What about RISCV_ISA_ZBB=y but the HW doesn't support Zbb? We have the same heavy generic fls64() issue. Let's improve this situation by checking Zbb extension and fall back to generic count_masked_bytes() if Zbb isn't supported. To remove non-necessary zero bits couting on RV32, we also replace the 'fls64(mask) >> 3' with '!mask ? 0 : ((__fls(mask) + 1) >> 3);' We will get similar performance improvement as previous commit for RISCV_ISA_ZBB=y but HW doesn't support Zbb. Signed-off-by: Jisheng Zhang --- arch/riscv/include/asm/word-at-a-time.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/word-at-a-time.h b/arch/riscv/include/asm/word-at-a-time.h index 1dcac57a73dd..f2d16c1eea8d 100644 --- a/arch/riscv/include/asm/word-at-a-time.h +++ b/arch/riscv/include/asm/word-at-a-time.h @@ -65,8 +65,9 @@ static inline long count_masked_bytes(long mask) static inline unsigned long find_zero(unsigned long mask) { - if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZBB)) - return fls64(mask) >> 3; + if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZBB) && + riscv_has_extension_likely(RISCV_ISA_EXT_ZBB)) + return !mask ? 0 : ((__fls(mask) + 1) >> 3); return count_masked_bytes(mask); } -- 2.53.0