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Wed, 09 Sep 2026 11:01:15 -0700 (PDT) X-Received: by 2002:a05:6820:4df3:b0:6be:46f4:2908 with SMTP id 006d021491bc7-6be46f43c91mr2959494eaf.55.1788976873782; Wed, 09 Sep 2026 11:01:13 -0700 (PDT) Received: from localhost ([50.35.44.179]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1435c2ae6b5sm280583c88.1.2026.09.09.11.01.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Sep 2026 11:01:12 -0700 (PDT) Date: Wed, 9 Sep 2026 10:59:54 -0700 From: Jonathan Cameron To: Jason Gunthorpe Cc: Nicolin Chen , will@kernel.org, robin.murphy@arm.com, joro@8bytes.org, bhelgaas@google.com, praan@google.com, kevin.tian@intel.com, kees@kernel.org, smostafa@google.com, baolu.lu@linux.intel.com, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, skaestle@nvidia.com, mmarrid@nvidia.com, skolothumtho@nvidia.com, bbiber@nvidia.com, harsha.v@oss.qualcomm.com Subject: Re: [PATCH v3 08/13] iommu/arm-smmu-v3: Disable PRI when no IRQ handler is registered Message-ID: <20260909105954.00002181@oss.qualcomm.com> In-Reply-To: <20260904141525.GT4157646@nvidia.com> References: <0b5282c7e850f1a1c650e43670899b4ef5335efd.1788222486.git.nicolinc@nvidia.com> <178846311318.1308030.4956293524348641228.b4-review@b4> <20260904141525.GT4157646@nvidia.com> Organization: Qualcomm X-Mailer: Claws Mail 4.4.0 (GTK 3.24.51; x86_64-w64-mingw32) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=M+997Sws c=1 sm=1 tr=0 ts=6aa19eec cx=c_pps a=Z3eh007fzM5o9awBa1HkYQ==:117 a=aNnz9XPx1a4JIXSYt2cE/A==:17 a=kj9zAlcOel0A:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=Ikd4Dj_1AAAA:8 a=nKlBY_KgISjqlfJ5XcQA:9 a=CjuIK1q_8ugA:10 a=eBU8X_Hb5SQ8N-bgNfv4:22 X-Proofpoint-GUID: CZu-nHFfRMQ66kUUUBAnx--SsJ0LW02Y X-Proofpoint-ORIG-GUID: CZu-nHFfRMQ66kUUUBAnx--SsJ0LW02Y X-Proofpoint-Spam-Info: AW1haW4tMjYwOTA5MDIwMSBTYWx0ZWRfX6WtiB/5TS1Gn WdA3rCFtrIImyO8cYCpzQOS2ZygtWxhD/5tahdmpAUHgBdm2S30+nu3aocpORQrEII/Qyj6XcpY qY8L5RQMOc6Q0WPYZ5QFYW/tbC3ERvc= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTA5MDIwMSBTYWx0ZWRfXwwtys9Xz4bZS vosWWrJE289G757ibAzAxaCpVJXvutJXTboDa40Qp++6Utj4l9QsECKBOC317Cr0xtfWlgJgMs1 l/n4g1msSuZ1sBXcW0ksqDaVWzpnJGMieYTX3hdHKuWrxmQr8CX2rJsGW92eky0Mmy1lP/cP6Y1 dZpeoWw2bjK+dB19kdsD8M8ovgdHWeIf3brvS2zexwzyiyQz1LmVV4gcsRf9HeBdiaZozMJvygx 5tGlfsoNf16p9g2Lur7PYilibqFlhAMwAxmK+dPV/zJBBXxbLHN40x0T5nd1w9S0n4i2BWe6179 wXUy94rDd6izAyCV8+tvbQmxIQazUyx8N2CD9G/K8AdUgxxjwqwLA3JzYcj7qtktsqCb1bU6j12 WQRhH4USspDoX3lFsEkB2VqlZcW1X7XH6MjemamXOv6JYTlnAlg6HbT5VAttodKVoWsvbrNKEFd VKWGl4XmgwhCy/XZ1GA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-08_03,2026-09-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 bulkscore=0 spamscore=0 phishscore=0 impostorscore=0 lowpriorityscore=0 suspectscore=0 clxscore=1015 priorityscore=1501 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609090201 On Fri, 4 Sep 2026 11:15:25 -0300 Jason Gunthorpe wrote: > On Thu, Sep 03, 2026 at 12:18:33PM -0700, Jonathan Cameron wrote: > > > arm_smmu_setup_irqs() has three failure paths that leave the priq without > > > a handler: a missing priq IRQ line, devm_request_threaded_irq() failure on > > > the priq IRQ, and devm_request_threaded_irq() failure on the combined IRQ. > > > Each path warned but kept ARM_SMMU_FEAT_PRI set in smmu->features. > > > > > > With FEAT_PRI still set, arm_smmu_setup_irqs() enables IRQ_CTRL_PRIQ_IRQEN > > > against a handler that does not exist, and a later change would then have > > > arm_smmu_probe_device() call pci_enable_pri() on PCIe endpoints, allowing > > > them to issue PRI Page Requests that pile up in the priq with no drainer. > > > Separately, arm_smmu_device_reset() has already enabled CR0_PRIQEN before > > > it invoked arm_smmu_setup_irqs(), so the hardware queue would stay enabled > > > regardless of what setup_irqs decides. > > > > > > Clear ARM_SMMU_FEAT_PRI in all three failure paths, so that subsequent code > > > treats PRI as unavailable. And disable CR0_PRIQEN after the setup function > > > returns. > > > > > > A kdump kernel cannot service page requests: strip FEAT_PRI when detecting > > > features, so downstream PRI setup is skipped. > > > > Dumb question - why can't a kdump kernel service page requests? > > I'm nowhere near familiar enough with that stuff and I suspect I'm not > > the only one who might be in that state and reading this series. > > Configuration choice, or a fundamental thing? > > The initial issue is the streams are left in whatever state the crash > kernel had them in, so it can be generating a bunch of PRIs with no > place to put them. > > Though eventually we may find a device where dropping them is not good > and they need to be NAK'd promptly.. > > But I think the real motivation here is to save memory in the kdump > kernel.. Got it, so design decision rather than fundamental. Maybe tweak that text to say "A kdump kernel doesn't service page request" ? > > Jason >