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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni Cc: Johan Alvarado , Mieczyslaw Nalewaj , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH net] net: dsa: realtek: rtl8365mb: let the SerDes PLL settle after the data-path reset Date: Wed, 9 Sep 2026 14:08:38 +0200 Message-ID: <20260909120838.33380-1-kuncy7@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260907191945.806751-1-kuncy7@gmail.com> References: <20260907191945.806751-1-kuncy7@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Withdrawing this one. The evidence behind it came entirely from a single Archer AX55 v1, and it was never separated from the chip-reset patch it was sent alongside: the cold-boot counts I quoted were measured with both applied, as Johan pointed out on the OpenWrt side. Since then the case for trusting that board has got weaker rather than stronger. It is four years old, it has one confirmed power supply fault behind it, its cold-boot behaviour differs from its warm-boot behaviour in a way Alvin rightly reads as out-of-spec supplies, and Johan cannot reproduce anything like it on an MR80X v2.20 with the same IPQ5018 and RTL8367S. The 98 ms wait may still be right - the vendor firmware does take it, and the constant is in the vendor SerDes init table - but "the vendor does it" is not on its own a reason to put a delay in a driver, and I have nothing else left to offer for it. If someone reproduces a half-alive SGMII link on hardware that is not suspect, this is easy to bring back. The chip-reset patch is respun separately as v3, retargeted at net-next and without the Fixes tag, for reasons set out there: https://lore.kernel.org/all/20260908174403.420507-1-kuncy7@gmail.com/ Sorry for the noise, and thanks to all of you for the time on it. Best regards, Stanislaw