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Thu, 10 Sep 2026 06:01:47 -0700 (PDT) X-Received: by 2002:a17:902:db07:b0:2db:5ea1:8b04 with SMTP id d9443c01a7336-2db5ea18e2amr338952815ad.5.1789045277098; Thu, 10 Sep 2026 06:01:17 -0700 (PDT) Received: from hu-apateriy-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2db1495b9f0sm88424805ad.20.2026.09.10.06.01.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Sep 2026 06:01:16 -0700 (PDT) From: Anurag Pateriya Date: Thu, 10 Sep 2026 18:30:44 +0530 Subject: [PATCH 2/2] soc: qcom: llcc: Add LLCC configuration for Nord Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260910-nord_llcc-v1-2-30fd1cca65fe@oss.qualcomm.com> References: <20260910-nord_llcc-v1-0-30fd1cca65fe@oss.qualcomm.com> In-Reply-To: <20260910-nord_llcc-v1-0-30fd1cca65fe@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Conor Dooley , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anurag Pateriya , zhangfei.gao@oss.qualcomm.com, shengchao.guo@oss.qualcomm.com X-Mailer: b4 0.13.0 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTEwMDE1NiBTYWx0ZWRfX1DXghkOrvQeR 7bsz9EUMII4PaCjcKzd76mxxSkJ28SXJIxGQVzKERnhTA9DDuowUK49EBQuby3p28wJ6dpcAP8r HAABECteeLUTFpivzar0s9MmXfasZlk= X-Proofpoint-GUID: h8IRdFtqcz4MjPRpayn8S2y4gX_ooKDw X-Authority-Analysis: v=2.4 cv=aef0Dhot c=1 sm=1 tr=0 ts=6aa2aa4c cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=22uKg8MptKaIaSBHXdMA:9 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTEwMDE1NiBTYWx0ZWRfX+v2pE9WokXDQ T+YZfaF+5lFLm2prc0ETMpMBu4xYOMNL9fphI8GVnc4F1szaJlEYFB+CApTRX9bg+ssVRvOkfzx tyr3LLXl2Q/YzKq/he86WSApy3bArTRNuadBvFj2lSCy52anyNIjSo3kVSGkZB7eL+2YWF2RYeI n38Tr4vUhXvMVVZXR9k4hsR45RMygK4f9Y9VlZha8/7Ffjl4ZVcK8rxThO9VSgEoMewZqQBMt2D DAtkYByNEHla9uNmstkw8LyPeKvmNB8xr0jWf+EDOAxDOkhW3eQ6AZOvJLcilUaAZO4nfhZ5pyR b6OEVrumeJgzvFg0HJfDTiCghTZzyB20pkO/qDi11ak1789ALGNCiUdsktxMfT28c7vuLxAirtg htVmTQOIrzX2vHbspP5WcpjZl5IbGedDU59SHZPmexSUtGK46slaihPiM9eINOidO0PMoT6HNTk FnLqKIxNJ9zjnfSmkOQ== X-Proofpoint-ORIG-GUID: h8IRdFtqcz4MjPRpayn8S2y4gX_ooKDw X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-10_04,2026-09-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 malwarescore=0 phishscore=0 priorityscore=1501 adultscore=0 lowpriorityscore=0 impostorscore=0 bulkscore=0 clxscore=1011 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609100156 Add the sub-cache table for Nord, derived from the Nord AU (Safe IVI) SCT table and limited to the POR use cases that have a unique SCID and a usecase ID in llcc-qcom.h. Nord has the CFG0/CFG1 pairs and the full ALGO_ALLOC0..3 set, so it uses the v6 register offsets. num_banks is set explicitly because LLCC_LB_CNT in LLCC_COMMON_STATUS0 is four bits wide and cannot report sixteen banks; a wrong count makes the driver map a bank aperture in place of the broadcast region and abort on the first broadcast read. no_edac is set because the bootloader leaves the LLCC EDAC registers locked, as on Glymur. Signed-off-by: Anurag Pateriya --- drivers/soc/qcom/llcc-qcom.c | 139 +++++++++++++++++++++++++++++++++++++ include/linux/soc/qcom/llcc-qcom.h | 2 + 2 files changed, 141 insertions(+) diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 5e45a10663c4..d7a42a8040a1 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -1054,6 +1054,128 @@ static const struct llcc_slice_config kaanapali_data[] = { }, }; +static const struct llcc_slice_config nord_data[] = { + { + .usecase_id = LLCC_CPUSS, + .slice_id = 1, + .max_cap = 3072, + .priority = 0, + .bonus_ways = 0xff, + .activate_on_init = true, + .write_scid_en = true, + .write_scid_cacheable_en = true, + .vict_prio = true, + }, { + .usecase_id = LLCC_CMPT, + .slice_id = 34, + .max_cap = 0, + .priority = 1, + .fixed_size = true, + .bonus_ways = 0xff, + .vict_prio = true, + }, { + .usecase_id = LLCC_GPUHTW, + .slice_id = 11, + .max_cap = 512, + .priority = 1, + .fixed_size = true, + .bonus_ways = 0xff, + .vict_prio = true, + }, { + .usecase_id = LLCC_GPU, + .slice_id = 12, + .max_cap = 2048, + .priority = 1, + .fixed_size = true, + .bonus_ways = 0xff, + .write_scid_en = true, + .write_scid_cacheable_en = true, + .vict_prio = true, + }, { + .usecase_id = LLCC_MMUHWT, + .slice_id = 13, + .max_cap = 1024, + .priority = 1, + .fixed_size = true, + .bonus_ways = 0xff, + .activate_on_init = true, + .vict_prio = true, + }, { + .usecase_id = LLCC_CAMFW, + .slice_id = 20, + .max_cap = 512, + .priority = 2, + .fixed_size = true, + .bonus_ways = 0xff, + .vict_prio = true, + }, { + .usecase_id = LLCC_ECC, + .slice_id = 26, + .max_cap = 1536, + .priority = 3, + .fixed_size = true, + .bonus_ways = 0xff, + .activate_on_init = true, + .write_scid_en = true, + .write_scid_cacheable_en = true, + .vict_prio = true, + }, { + .usecase_id = LLCC_WRCACHE, + .slice_id = 31, + .max_cap = 2048, + .priority = 1, + .fixed_size = true, + .bonus_ways = 0xff, + .activate_on_init = true, + .vict_prio = true, + }, { + .usecase_id = LLCC_LCPDARE, + .slice_id = 30, + .max_cap = 512, + .priority = 3, + .fixed_size = true, + .bonus_ways = 0xff, + .activate_on_init = true, + .alloc_oneway_en = true, + .vict_prio = true, + }, { + .usecase_id = LLCC_COMPUTE1, + .slice_id = 22, + .max_cap = 0, + .priority = 1, + .fixed_size = true, + .bonus_ways = 0xff, + .vict_prio = true, + }, { + .usecase_id = LLCC_PCIE_TCU, + .slice_id = 15, + .max_cap = 0, + .priority = 1, + .fixed_size = true, + .bonus_ways = 0xff, + .activate_on_init = true, + .vict_prio = true, + }, { + .usecase_id = LLCC_GPU_LITTLE, + .slice_id = 9, + .max_cap = 2048, + .priority = 1, + .fixed_size = true, + .bonus_ways = 0xff, + .write_scid_en = true, + .write_scid_cacheable_en = true, + .vict_prio = true, + }, { + .usecase_id = LLCC_GPUHTW_LITTLE, + .slice_id = 14, + .max_cap = 512, + .priority = 1, + .fixed_size = true, + .bonus_ways = 0xff, + .vict_prio = true, + }, +}; + static const struct llcc_slice_config sa8775p_data[] = { { .usecase_id = LLCC_CPUSS, @@ -4484,6 +4606,17 @@ static const struct qcom_llcc_config glymur_cfg[] = { }, }; +static const struct qcom_llcc_config nord_cfg[] = { + { + .sct_data = nord_data, + .size = ARRAY_SIZE(nord_data), + .reg_offset = llcc_v6_reg_offset, + .edac_reg_offset = &llcc_v6_edac_reg_offset, + .num_banks = 16, + .no_edac = true, + }, +}; + static const struct qcom_llcc_config qcs615_cfg[] = { { .sct_data = qcs615_data, @@ -4751,6 +4884,11 @@ static const struct qcom_sct_config glymur_cfgs = { .num_config = ARRAY_SIZE(glymur_cfg), }; +static const struct qcom_sct_config nord_cfgs = { + .llcc_config = nord_cfg, + .num_config = ARRAY_SIZE(nord_cfg), +}; + static const struct qcom_sct_config qcs615_cfgs = { .llcc_config = qcs615_cfg, .num_config = ARRAY_SIZE(qcs615_cfg), @@ -5693,6 +5831,7 @@ static const struct of_device_id qcom_llcc_of_match[] = { { .compatible = "qcom,hawi-llcc", .data = &hawi_sct_cfgs }, { .compatible = "qcom,ipq5424-llcc", .data = &ipq5424_cfgs}, { .compatible = "qcom,kaanapali-llcc", .data = &kaanapali_cfgs}, + { .compatible = "qcom,nord-llcc", .data = &nord_cfgs}, { .compatible = "qcom,qcs615-llcc", .data = &qcs615_cfgs}, { .compatible = "qcom,qcs8300-llcc", .data = &qcs8300_cfgs}, { .compatible = "qcom,qdu1000-llcc", .data = &qdu1000_cfgs}, diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h index 1ccc429401e8..713cb0221b14 100644 --- a/include/linux/soc/qcom/llcc-qcom.h +++ b/include/linux/soc/qcom/llcc-qcom.h @@ -74,6 +74,7 @@ #define LLCC_CAMSRTIP 73 #define LLCC_CAMRTRF 74 #define LLCC_CAMSRTRF 75 +#define LLCC_GPU_LITTLE 80 #define LLCC_OOBM_NS 81 #define LLCC_OOBM_S 82 #define LLCC_VIDEO_APV 83 @@ -85,6 +86,7 @@ #define LLCC_CAM_OFE_STROV 93 #define LLCC_CPUSS_HEU 94 #define LLCC_PCIE_TCU 97 +#define LLCC_GPUHTW_LITTLE 98 #define LLCC_MDM_PNG_FIXED 100 #define LLCC_PPE_RXDESC 101 #define LLCC_PPE_RXFILL 102 -- 2.43.0