[PATCH net v2] octeontx2-af: Handle pool context address update in aura WRITE operation

[<nshettyj@marvell.com>]

From: Ashwin Sekhar T K <asekhar@marvell.com>

The NPA AQ WRITE operation for aura context was not translating the
pool_id in aura.pool_addr to the actual pool context IOVA, unlike the
INIT path which already did this correctly.

Add a helper npa_aura_translate_pool_addr() that validates pool_ctx,
checks bounds, and performs the pool_id to IOVA translation. Use it
in both the WRITE and INIT paths to fix the missing translation and
avoid code duplication.

Fixes: 4a3581cd5995 ("octeontx2-af: NPA AQ instruction enqueue support")
Signed-off-by: Nitin Shetty J <nshettyj@marvell.com>
Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
---
changes in v2:
 - Reject partial aura_mask.pool_addr writes; only translate
   pool_addr to a real pool context address when the mask
   selects the full word
---
 .../ethernet/marvell/octeontx2/af/rvu_npa.c   | 35 +++++++++++++++----
 1 file changed, 29 insertions(+), 6 deletions(-)

diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c
index e2a33e46b48a..775a3f0b88bd 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c
@@ -5,6 +5,7 @@
  *
  */
 #include <linux/bitfield.h>
+#include <linux/limits.h>
 #include <linux/module.h>
 #include <linux/pci.h>
 
@@ -58,6 +59,19 @@ static int npa_aq_enqueue_wait(struct rvu *rvu, struct rvu_block *block,
 	return 0;
 }
 
+static int npa_aura_translate_pool_addr(struct rvu_pfvf *pfvf, u64 *pool_addr)
+{
+	if (!pfvf->pool_ctx)
+		return NPA_AF_ERR_AQ_ENQUEUE;
+
+	if (*pool_addr >= pfvf->pool_ctx->qsize)
+		return NPA_AF_ERR_PARAM;
+
+	*pool_addr = pfvf->pool_ctx->iova +
+		     (*pool_addr * pfvf->pool_ctx->entry_sz);
+	return 0;
+}
+
 int rvu_npa_aq_enq_inst(struct rvu *rvu, struct npa_aq_enq_req *req,
 			struct npa_aq_enq_rsp *rsp)
 {
@@ -116,6 +130,18 @@ int rvu_npa_aq_enq_inst(struct rvu *rvu, struct npa_aq_enq_req *req,
 	case NPA_AQ_INSTOP_WRITE:
 		/* Copy context and write mask */
 		if (req->ctype == NPA_AQ_CTYPE_AURA) {
+			/* Translate pool_addr only on a full-word write,
+			 * partial masks aren't valid pool_id updates.
+			 */
+			if (req->aura_mask.pool_addr == U64_MAX) {
+				rc = npa_aura_translate_pool_addr(pfvf,
+								  &req->aura.pool_addr);
+				if (rc)
+					break;
+			} else if (req->aura_mask.pool_addr) {
+				rc = NPA_AF_ERR_PARAM;
+				break;
+			}
 			memcpy(mask, &req->aura_mask,
 			       sizeof(struct npa_aura_s));
 			memcpy(ctx, &req->aura, sizeof(struct npa_aura_s));
@@ -127,13 +153,10 @@ int rvu_npa_aq_enq_inst(struct rvu *rvu, struct npa_aq_enq_req *req,
 		break;
 	case NPA_AQ_INSTOP_INIT:
 		if (req->ctype == NPA_AQ_CTYPE_AURA) {
-			if (req->aura.pool_addr >= pfvf->pool_ctx->qsize) {
-				rc = NPA_AF_ERR_AQ_FULL;
+			rc = npa_aura_translate_pool_addr(pfvf,
+							  &req->aura.pool_addr);
+			if (rc)
 				break;
-			}
-			/* Set pool's context address */
-			req->aura.pool_addr = pfvf->pool_ctx->iova +
-			(req->aura.pool_addr * pfvf->pool_ctx->entry_sz);
 			memcpy(ctx, &req->aura, sizeof(struct npa_aura_s));
 		} else { /* POOL's context */
 			memcpy(ctx, &req->pool, sizeof(struct npa_pool_s));
-- 
2.48.1