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Thu, 10 Sep 2026 03:25:03 -0700 From: Tariq Toukan To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , , Paolo Abeni CC: Edward Srouji , Gal Pressman , "Jason Gunthorpe" , Leon Romanovsky , open list , , Maher Sanalla , Mark Bloch , Or Har-Toov , Saeed Mahameed , Shay Drori , Tariq Toukan Subject: [PATCH net 0/5] net/mlx5: fixes for LAG max_tx_speed update flow Date: Thu, 10 Sep 2026 13:24:27 +0300 Message-ID: <20260910102432.3845360-1-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF00022570:EE_|SN7PR12MB8819:EE_ X-MS-Office365-Filtering-Correlation-Id: 2cbc31fc-913c-452a-69ea-08df0f25d2e1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|1800799024|7416014|376014|23010399003|82310400026|10067099003|56012099006|11063799006|6133799003|18002099003; X-Microsoft-Antispam-Message-Info: goz8bELzuy5Lzi6cvyZPLOUL/uy9m5hG1Y5BMZO2kOLE0Hf6X9cEbH5Czq+YUZVjCQhqdfoujZOG78SGBXtnB5iG7Zq1t5Uct3n5qd6c5Q4NIDgsM+vsRgUZwQ+Yh+diJ9ANbekdj2/P010ltLhgCvXo8fGKlyL9tEi3+/XD17MDw8Z5yfbe5arCj4Bh7Cvno/qtob5GaYR0MPhKSjwha1yYb4nLN63owCzv2IbOO9fCFoL7FGRcYoTwL3J9E7dOAqXdjlv+Gv9TZ/CFK7bICYlrxfxFx7tB4qoyeuNJ245APoLVJ5YBAxZEvg7paLPlzHUiY8e4zROyKOFZrHluH1IFl+66x+p8ccFMVZrMsw4ZGnNowhkcADc4FdlysAIv27wN3g1jWfYATPXx5iUCpb+yUS2b6RWizFZuNd9qqKSmxmDPwTpUDVmiebNFwvHwhPj96bUa5UH41UH/E9LjfxGfkPeSh7IFQeJnylYUYlAwYd8gZ6xgyQfLjfUwYylTShnVYvNAdMrmGgQd7IwB4k+w1wObuD5fTKiaR3BEtiNvQR/VvEgQ8633lgFVy4A0xOg9XMkXA5TYuHwUgLtY/qbT/pyd7JLYZM5ON8WWFEevFOvyunp/D2IhRtFeFWXLYlj0fCwcdTJnlKEavHjd9mLVRzi6YpOgitPEpfuVH76r7mJnVxula6ZDVyh+6SdV X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(1800799024)(7416014)(376014)(23010399003)(82310400026)(10067099003)(56012099006)(11063799006)(6133799003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 3Gg1R48fW9ASBVjzELOfdBVce+VpSMx8sAb/ivUDvmniOWcLOTwv9ty3pPw8qZHWehIooGer50Gug3PIDVEz71unhFuovi7XOfwpL/zBjmQSZR4EZXxvUAQRQHA8Gb8MvKYyHnXEP0rwZZcLXTRyuxYEgz2uIhY5Nmbi2XyHqCo092pdXWf9EURNtdMeW/plo05n4dXiVucNz2VfXkDg2tFFDl2J2Glu9uUdnCBNKyQXyZuNHhPFmrFE6fwkfbVeUzPTYmbGvTsQAuUkcbfwQX1WeMwk4KOWUvdGXKqhyf9FvbSFmbJPkuZoRhw2ccavYvc0HswH4qpfCf3jn273+pE2jRpI+opoV60e8slyHCCwAV/wE6/9+FCvtBVegNIyqKdFj7EA8hRGGMI8+zEoDn8lDdbmnaKw1UOv3un/WqW70LRviBaU86vST8Sa3VqD X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Sep 2026 10:25:23.4279 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2cbc31fc-913c-452a-69ea-08df0f25d2e1 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00022570.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB8819 Hi, Commit 50f1d188c580 ("net/mlx5: Propagate LAG effective max_tx_speed to vports") added a mechanism that computes the aggregated LAG TX speed and programs it into each vport's max_tx_speed via MODIFY_VPORT_STATE. This series by Or fixes bugs found in that flow. The bugs: 1. Down ports were counted into the effective aggregate speed. When a port goes down, PTYS eth_proto_oper is not necessary 0. 2. The aggregate was not limited by the NIC's PCIe bandwidth. It was taken from the bond speed, which is calculated from PTYS, and PTYS is not bounded by the PCI bandwidth of the NIC. FW initializes max_tx_speed to the minimum of the port speed and the PCIe bandwidth, so modifying it with a value computed by different rules changes the meaning of the field rather than updating it. 3. MPESW teardown never reset the vport speeds, leaving stale values after teardown. 4. RoCE LAG never told the RDMA layer about speed changes. The NIC is considered to be in a bare metal configuration, without a valid or enabled eswitch, so there are no VF, SF or PF rep vports to modify and no event of speed change was raised. Patch #1 splits the LAG aggregate speed into an operative and a max helper, so that each can filter on port state on its own. Patch #2 resets the vport speed on MPESW teardown. Patch #3 caches the TX-enabled aggregate speed and programs that into the vports, instead of reading it back from the bond netdev. Patch #4 limits the aggregated TX speed by the NIC's PCIe bandwidth. Patch #5 notifies the RDMA layer of RoCE LAG speed changes via a new driver event. Regards, Tariq Or Har-Toov (5): net/mlx5: Lag, split aggregate speed into oper and max helpers net/mlx5: Lag, reset vport speed on teardown {RDMA,net}/mlx5: cache and use TX-enabled aggregate speed for vports net/mlx5: Lag, limit aggregated TX speed by PCIe bandwidth {RDMA,net}/mlx5: notify RoCE LAG speed change via driver event drivers/infiniband/hw/mlx5/main.c | 12 +- drivers/net/ethernet/mellanox/mlx5/core/dev.c | 20 +++ .../net/ethernet/mellanox/mlx5/core/lag/lag.c | 159 +++++++++++++++--- .../net/ethernet/mellanox/mlx5/core/lag/lag.h | 16 +- .../ethernet/mellanox/mlx5/core/mlx5_core.h | 1 + include/linux/mlx5/device.h | 1 + include/linux/mlx5/driver.h | 1 + 7 files changed, 181 insertions(+), 29 deletions(-) base-commit: 00f9fbc12320253bfc576fb7539d860029c82d0f -- 2.44.0