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Thu, 10 Sep 2026 08:54:05 -0700 (PDT) Received: from DESKTOP-TIT0J8O.dm.ae ([49.47.196.141]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1432435648esm64763657c88.5.2026.09.10.08.54.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Sep 2026 08:54:04 -0700 (PDT) From: Ahmed Naseef To: linux-mtd@lists.infradead.org Cc: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , linux-kernel@vger.kernel.org, Ahmed Naseef Subject: [PATCH] mtd: spinand: Only touch the QE bit on chips that have one Date: Thu, 10 Sep 2026 19:53:55 +0400 Message-Id: <20260910155355.3534491-1-naseefkm@gmail.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Since commit be0b86c648bf ("mtd: spinand: Gather all the bus interface steps in one single function") spinand_init_quad_enable() is called unconditionally and clears bit 0 of the configuration register even on chips without SPINAND_HAS_QE_BIT. On such chips that bit can have another meaning: on the Winbond W25N02KV it is H-DIS (Hold Disable, default 1), and clearing it enables the /HOLD function, after which erase and program operations silently stop taking effect on MT7986 boards. Only program the QE bit when the chip declares SPINAND_HAS_QE_BIT, as before. Fixes: be0b86c648bf ("mtd: spinand: Gather all the bus interface steps in one single function") Cc: stable@vger.kernel.org Assisted-by: Claude Code:claude-opus-5 Signed-off-by: Ahmed Naseef --- drivers/mtd/nand/spi/core.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index 43bbe2629b85..9fc1512e4fe2 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -1781,7 +1781,7 @@ static int spinand_detect(struct spinand_device *spinand) static int spinand_configure_chip(struct spinand_device *spinand) { bool odtr = false, quad_enable = false; - int ret; + int ret = 0; if (spinand->odtr_op_templates.read_cache && spinand->odtr_op_templates.write_cache && @@ -1808,16 +1808,21 @@ static int spinand_configure_chip(struct spinand_device *spinand) } try_ssdr: + /* + * Only touch the QE bit on chips that actually have one. On other + * chips bit 0 of the configuration register may have a different + * meaning (e.g. H-DIS on the Winbond W25N02KV). + */ if (spinand->flags & SPINAND_HAS_QE_BIT) { if (spinand->ssdr_op_templates.read_cache->data.buswidth == 4 || spinand->ssdr_op_templates.write_cache->data.buswidth == 4 || spinand->ssdr_op_templates.update_cache->data.buswidth == 4) quad_enable = true; - } - ret = spinand_init_quad_enable(spinand, quad_enable); - if (ret) - return ret; + ret = spinand_init_quad_enable(spinand, quad_enable); + if (ret) + return ret; + } if (spinand->configure_chip) { ret = spinand->configure_chip(spinand, SSDR); base-commit: 21f027016b1290d13c30b198ae7a00e6b3d1d5a5 -- 2.34.1