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Thu, 10 Sep 2026 12:46:18 -0700 (PDT) Received: from ryzen.lan ([2601:644:8000:7a86::e35]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-530ca50cd05sm1174131cf.29.2026.09.10.12.46.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Sep 2026 12:46:18 -0700 (PDT) From: Rosen Penev To: dmaengine@vger.kernel.org Cc: Vinod Koul , Frank Li , Rosen Penev , linux-kernel@vger.kernel.org (open list) Subject: [PATCHv2] dmaengine: fsl_raid: switch __b32 to u32 Date: Thu, 10 Sep 2026 12:46:16 -0700 Message-ID: <20260910194616.34760-1-rosenp@gmail.com> X-Mailer: git-send-email 2.55.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The register maps in fsl_raid.h annotate every field as __be32, but they are accessed only through ioread32be()/iowrite32be(), which already perform the byte swap and take plain u32 __iomem pointers. The __be32 annotation therefore makes sparse reject each access: drivers/dma/fsl_raid.c:116:17: sparse: incorrect type in argument 1 (different base types) ... got restricted __be32 [noderef] __iomem * Drop __be32 from struct fsl_re_ctrl and struct fsl_re_chan_cfg; the descriptor/CDB structures written via cpu_to_be32() keep their annotations. Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202608200637.ro1CqMxi-lkp@intel.com/ Fixes: 68b7fbc23529 ("dma: fsl_raid: keep MMIO bases as void __iomem and cast at access") Assisted-by: opencode:deepseek-v4-flash-free Signed-off-by: Rosen Penev Reviewed-by: Frank Li --- v2: split patch up. drivers/dma/fsl_raid.h | 54 +++++++++++++++++++++--------------------- 1 file changed, 27 insertions(+), 27 deletions(-) diff --git a/drivers/dma/fsl_raid.h b/drivers/dma/fsl_raid.h index adbfede330a7..6fde5192ab77 100644 --- a/drivers/dma/fsl_raid.h +++ b/drivers/dma/fsl_raid.h @@ -110,59 +110,59 @@ struct fsl_re_ctrl { /* General Configuration Registers */ - __be32 global_config; /* Global Configuration Register */ + u32 global_config; /* Global Configuration Register */ u8 rsvd1[4]; - __be32 galois_field_config; /* Galois Field Configuration Register */ + u32 galois_field_config; /* Galois Field Configuration Register */ u8 rsvd2[4]; - __be32 jq_wrr_config; /* WRR Configuration register */ + u32 jq_wrr_config; /* WRR Configuration register */ u8 rsvd3[4]; - __be32 crc_config; /* CRC Configuration register */ + u32 crc_config; /* CRC Configuration register */ u8 rsvd4[228]; - __be32 system_reset; /* System Reset Register */ + u32 system_reset; /* System Reset Register */ u8 rsvd5[252]; - __be32 global_status; /* Global Status Register */ + u32 global_status; /* Global Status Register */ u8 rsvd6[832]; - __be32 re_liodn_base; /* LIODN Base Register */ + u32 re_liodn_base; /* LIODN Base Register */ u8 rsvd7[1712]; - __be32 re_version_id; /* Version ID register of RE */ - __be32 re_version_id_2; /* Version ID 2 register of RE */ + u32 re_version_id; /* Version ID register of RE */ + u32 re_version_id_2; /* Version ID 2 register of RE */ u8 rsvd8[512]; - __be32 host_config; /* Host I/F Configuration Register */ + u32 host_config; /* Host I/F Configuration Register */ }; struct fsl_re_chan_cfg { /* Registers for JR interface */ - __be32 jr_config_0; /* Job Queue Configuration 0 Register */ - __be32 jr_config_1; /* Job Queue Configuration 1 Register */ - __be32 jr_interrupt_status; /* Job Queue Interrupt Status Register */ + u32 jr_config_0; /* Job Queue Configuration 0 Register */ + u32 jr_config_1; /* Job Queue Configuration 1 Register */ + u32 jr_interrupt_status; /* Job Queue Interrupt Status Register */ u8 rsvd1[4]; - __be32 jr_command; /* Job Queue Command Register */ + u32 jr_command; /* Job Queue Command Register */ u8 rsvd2[4]; - __be32 jr_status; /* Job Queue Status Register */ + u32 jr_status; /* Job Queue Status Register */ u8 rsvd3[228]; /* Input Ring */ - __be32 inbring_base_h; /* Inbound Ring Base Address Register - High */ - __be32 inbring_base_l; /* Inbound Ring Base Address Register - Low */ - __be32 inbring_size; /* Inbound Ring Size Register */ + u32 inbring_base_h; /* Inbound Ring Base Address Register - High */ + u32 inbring_base_l; /* Inbound Ring Base Address Register - Low */ + u32 inbring_size; /* Inbound Ring Size Register */ u8 rsvd4[4]; - __be32 inbring_slot_avail; /* Inbound Ring Slot Available Register */ + u32 inbring_slot_avail; /* Inbound Ring Slot Available Register */ u8 rsvd5[4]; - __be32 inbring_add_job; /* Inbound Ring Add Job Register */ + u32 inbring_add_job; /* Inbound Ring Add Job Register */ u8 rsvd6[4]; - __be32 inbring_cnsmr_indx; /* Inbound Ring Consumer Index Register */ + u32 inbring_cnsmr_indx; /* Inbound Ring Consumer Index Register */ u8 rsvd7[220]; /* Output Ring */ - __be32 oubring_base_h; /* Outbound Ring Base Address Register - High */ - __be32 oubring_base_l; /* Outbound Ring Base Address Register - Low */ - __be32 oubring_size; /* Outbound Ring Size Register */ + u32 oubring_base_h; /* Outbound Ring Base Address Register - High */ + u32 oubring_base_l; /* Outbound Ring Base Address Register - Low */ + u32 oubring_size; /* Outbound Ring Size Register */ u8 rsvd8[4]; - __be32 oubring_job_rmvd; /* Outbound Ring Job Removed Register */ + u32 oubring_job_rmvd; /* Outbound Ring Job Removed Register */ u8 rsvd9[4]; - __be32 oubring_slot_full; /* Outbound Ring Slot Full Register */ + u32 oubring_slot_full; /* Outbound Ring Slot Full Register */ u8 rsvd10[4]; - __be32 oubring_prdcr_indx; /* Outbound Ring Producer Index */ + u32 oubring_prdcr_indx; /* Outbound Ring Producer Index */ }; /* -- 2.55.0