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Thu, 10 Sep 2026 16:17:05 -0700 (PDT) Received: from hu-mohs-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-33ba4f7390csm1204374eec.26.2026.09.10.16.17.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Sep 2026 16:17:05 -0700 (PDT) From: Mohammad Rafi Shaik To: Srinivas Kandagatla , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liam Girdwood , Mark Brown Cc: linux-sound@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Harendra Gautam Subject: [PATCH v2 3/9] arm64: dts: qcom: shikra: Add QAIF CPU node for audio Date: Fri, 11 Sep 2026 04:46:36 +0530 Message-Id: <20260910231642.1794948-4-mohammad.rafi.shaik@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260910231642.1794948-1-mohammad.rafi.shaik@oss.qualcomm.com> References: <20260910231642.1794948-1-mohammad.rafi.shaik@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTEwMDI5MyBTYWx0ZWRfX4mL2zSSkc772 JUe1M1aAQvVXRa+QHE4LzdfVD+eabx1DFL60z3zoO4SRHstRSeJpKHkLfmJbo0qzXEZnwsmCnEX NKvu2wzIoMHk5N9KWU5AShgZfxWl6rff1QEUHR5m7yG/fapWo/UmRHYRxOWQ7sbHNEd286nCd4o gRUb5ci17TEfnoKcYF87LVY1mkUabrBHD+S/ucxWiML2xsM451p67uRbORDyZai+rjV2aGUNUCt Deh6cA6bEVwKgkaEpdst8ShK7dZpVLvVhivvcPFS/tsLYLnqTIOhePtSz++QfCKDzUDRccTF9rj MPmZEiWtcurpCndvfmanZDfNuHrD6GKV2YpfRXNf4JAlkozMDppwOhz/RECspcx1Fl+RvI29fOf 5iqp44YXF8brGluK1Qx0f31vcr3gSQCng8PVoMgbB1SRE0LPXzu0dVMymD7UWJIeiwk+3EXbq0c iVWSFV204Bod0ZDbbQQ== X-Proofpoint-Spam-Info: AW1haW4tMjYwOTEwMDI5MyBTYWx0ZWRfX0hZQ4hfoMLgl q+6le3MqLntY0Zp8ZXnue0iB8LcxhCuahp11bjHGm2cLuhtnNrtZENfzaCBypLX1JKhMv7OWH6w yYhX5r00YgsGKUnEXboEdi++kVoBQZY= X-Proofpoint-GUID: ZIKs8ExffSGdwqmeAsiwW39IcOnvZ4WJ X-Authority-Analysis: v=2.4 cv=TupzFzXh c=1 sm=1 tr=0 ts=6aa33a73 cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=SNQ4sQprfOKLKwPE6BEA:9 a=mQ_c8vxmzFEMiUWkPHU9:22 X-Proofpoint-ORIG-GUID: ZIKs8ExffSGdwqmeAsiwW39IcOnvZ4WJ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-10_07,2026-09-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 malwarescore=0 lowpriorityscore=0 clxscore=1015 bulkscore=0 suspectscore=0 phishscore=0 priorityscore=1501 impostorscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609100293 Add the QAIF CPU endpoint in shikra.dtsi so board files can connect LPASS front-end links to backend codecs. Describe the MMIO region, interrupt, IOMMU mapping and required clocks for the QAIF block. Keep the node disabled at SoC level; board dts files enable and consume it in subsequent patches. Co-developed-by: Harendra Gautam Signed-off-by: Harendra Gautam Signed-off-by: Mohammad Rafi Shaik --- arch/arm64/boot/dts/qcom/shikra.dtsi | 35 ++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index b8a13462771a..52b71790becb 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -15,6 +15,7 @@ #include #include #include +#include #include / { @@ -3486,6 +3487,40 @@ cti@9900000 { label = "cti_apss_2"; }; + qaif_cpu: audio@a000000 { + compatible = "qcom,shikra-qaif-cpu"; + reg = <0x0 0x0a000000 0x0 0x20000>; + + interrupts = ; + + clocks = <&gcc GCC_LPASS_CONFIG_CLK>, + <&gcc GCC_LPASS_CORE_AXIM_CLK>, + <&audiocorecc AUDIO_CORE_CC_AUD_DMA_CLK>, + <&audiocorecc AUDIO_CORE_CC_AUD_DMA_MEM_CLK>, + <&audiocorecc AUDIO_CORE_CC_BUS_CLK>, + <&audiocorecc AUDIO_CORE_CC_AIF_IF0_IBIT_CLK>, + <&audiocorecc AUDIO_CORE_CC_AIF_IF1_IBIT_CLK>, + <&audiocorecc AUDIO_CORE_CC_AIF_IF2_IBIT_CLK>, + <&audiocorecc AUDIO_CORE_CC_AIF_IF3_IBIT_CLK>; + clock-names = "lpass_config", + "lpass_core_axim", + "aud_dma", + "aud_dma_mem", + "bus", + "aif_if0_ibit", + "aif_if1_ibit", + "aif_if2_ibit", + "aif_if3_ibit"; + + iommus = <&apps_smmu 0x1c0 0x0>; + + #sound-dai-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + audiocorecc: clock-controller@a0a0000 { compatible = "qcom,shikra-audiocorecc"; reg = <0x0 0x0a0a0000 0x0 0x10000>; -- 2.34.1