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From: Juergen Gross <jgross@suse.com>
To: linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org
Cc: Juergen Gross <jgross@suse.com>, David Airlie <airlied@redhat.com>
Subject: [PATCH v3 05/13] agp/nvidia: Stop using 32-bit MSR interfaces
Date: Fri, 11 Sep 2026 09:45:22 +0200	[thread overview]
Message-ID: <20260911074530.3140830-6-jgross@suse.com> (raw)
In-Reply-To: <20260911074530.3140830-1-jgross@suse.com>

The 32-bit MSR interfaces rdmsr() and wrmsr() are planned to be
removed. Use the related 64-bit variants instead.

Signed-off-by: Juergen Gross <jgross@suse.com>
---
 drivers/char/agp/nvidia-agp.c | 32 +++++++++++++++-----------------
 1 file changed, 15 insertions(+), 17 deletions(-)

diff --git a/drivers/char/agp/nvidia-agp.c b/drivers/char/agp/nvidia-agp.c
index 4787391bb6b4..3e760bc00afa 100644
--- a/drivers/char/agp/nvidia-agp.c
+++ b/drivers/char/agp/nvidia-agp.c
@@ -65,22 +65,20 @@ static int nvidia_fetch_size(void)
 
 static int nvidia_init_iorr(u32 base, u32 size)
 {
-	u32 base_hi, base_lo;
-	u32 mask_hi, mask_lo;
-	u32 sys_hi, sys_lo;
+	struct msr base_msr, mask_msr, sys_msr;
 	u32 iorr_addr, free_iorr_addr;
 
 	/* Find the iorr that is already used for the base */
 	/* If not found, determine the uppermost available iorr */
 	free_iorr_addr = AMD_K7_NUM_IORR;
 	for (iorr_addr = 0; iorr_addr < AMD_K7_NUM_IORR; iorr_addr++) {
-		rdmsr(IORR_BASE0 + 2 * iorr_addr, base_lo, base_hi);
-		rdmsr(IORR_MASK0 + 2 * iorr_addr, mask_lo, mask_hi);
+		rdmsrq(IORR_BASE0 + 2 * iorr_addr, base_msr.q);
+		rdmsrq(IORR_MASK0 + 2 * iorr_addr, mask_msr.q);
 
-		if ((base_lo & 0xfffff000) == (base & 0xfffff000))
+		if ((base_msr.l & 0xfffff000) == (base & 0xfffff000))
 			break;
 
-		if ((mask_lo & 0x00000800) == 0)
+		if ((mask_msr.l & 0x00000800) == 0)
 			free_iorr_addr = iorr_addr;
 	}
 
@@ -89,16 +87,16 @@ static int nvidia_init_iorr(u32 base, u32 size)
 		if (iorr_addr >= AMD_K7_NUM_IORR)
 			return -EINVAL;
 	}
-    base_hi = 0x0;
-    base_lo = (base & ~0xfff) | 0x18;
-    mask_hi = 0xf;
-    mask_lo = ((~(size - 1)) & 0xfffff000) | 0x800;
-    wrmsr(IORR_BASE0 + 2 * iorr_addr, base_lo, base_hi);
-    wrmsr(IORR_MASK0 + 2 * iorr_addr, mask_lo, mask_hi);
-
-    rdmsr(SYSCFG, sys_lo, sys_hi);
-    sys_lo |= 0x00100000;
-    wrmsr(SYSCFG, sys_lo, sys_hi);
+    base_msr.h = 0x0;
+    base_msr.l = (base & ~0xfff) | 0x18;
+    mask_msr.h = 0xf;
+    mask_msr.l = ((~(size - 1)) & 0xfffff000) | 0x800;
+    wrmsrq(IORR_BASE0 + 2 * iorr_addr, base_msr.q);
+    wrmsrq(IORR_MASK0 + 2 * iorr_addr, mask_msr.q);
+
+    rdmsrq(SYSCFG, sys_msr.q);
+    sys_msr.l |= 0x00100000;
+    wrmsrq(SYSCFG, sys_msr.q);
 
 	return 0;
 }
-- 
2.55.0


  parent reply	other threads:[~2026-09-11  7:46 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-11  7:45 [PATCH v3 00/13] x86/msr: Drop " Juergen Gross
2026-09-11  7:45 ` [PATCH v3 01/13] x86/cpu: Fix coding style violation Juergen Gross
2026-09-11  7:45 ` [PATCH v3 02/13] x86/msr: Remove wrmsr_safe() Juergen Gross
2026-09-11  7:45 ` [PATCH v3 03/13] x86/msr: Remove rdmsr_safe() Juergen Gross
2026-09-11  7:45 ` [PATCH v3 04/13] drivers/ata: Stop using 32-bit MSR interfaces Juergen Gross
2026-09-11  7:45 ` Juergen Gross [this message]
2026-09-11  7:45 ` [PATCH v3 06/13] fbdev/geode: " Juergen Gross
2026-09-11  7:45 ` [PATCH v3 07/13] hw_random/via-rng: " Juergen Gross
2026-09-11  7:45 ` [PATCH v3 08/13] drivers/gpio: " Juergen Gross
2026-09-11  7:45 ` [PATCH v3 09/13] drivers/misc: " Juergen Gross
2026-09-11  7:45 ` [PATCH v3 10/13] x86/msr: Remove wrmsr() Juergen Gross
2026-09-11  7:45 ` [PATCH v3 11/13] x86/msr: Remove rdmsr() Juergen Gross
2026-09-11  7:45 ` [PATCH v3 12/13] treewide: convert rdmsrq() from a macro to an inline function Juergen Gross
2026-09-11  9:37   ` Ilpo Järvinen
2026-09-13  5:36     ` Jürgen Groß
2026-09-11 10:11   ` Rafael J. Wysocki (Intel)
2026-09-11 13:22   ` Sean Christopherson
2026-09-14 15:54   ` Reinette Chatre
2026-09-11  7:45 ` [PATCH v3 13/13] x86/msr: Simplify some rdmsrq() use cases Juergen Gross
2026-09-11 13:20   ` Sean Christopherson

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