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[83.28.44.95]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49e60adaee4sm134624405e9.14.2026.09.11.11.11.15 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Fri, 11 Sep 2026 11:11:16 -0700 (PDT) Date: Fri, 11 Sep 2026 20:11:13 +0200 From: Michal Pecio To: Fabio Estevam Cc: gregkh@linuxfoundation.org, mathias.nyman@intel.com, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, parth.pancholi@toradex.com, francesco.dolcini@toradex.com Subject: Re: [PATCH 3/3] usb: xhci-pci: Put PWRON_POLARITY on a defined state Message-ID: <20260911201113.42cce0a6.michal.pecio@gmail.com> In-Reply-To: References: <20260909125842.528340-1-festevam@gmail.com> <20260909125842.528340-3-festevam@gmail.com> <20260909164339.7252469b.michal.pecio@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable On Fri, 11 Sep 2026 10:58:27 -0300, Fabio Estevam wrote: > Hi Michal, >=20 > On Wed, Sep 9, 2026 at 11:43=E2=80=AFAM Michal Pecio wrote: > > > > On Wed, 9 Sep 2026 09:58:42 -0300, Fabio Estevam wrote: =20 > > > Currently, TUSB73X0_PWRON_POLARITY is set when the > > > "ti,pwron-active-high" is present. > > > > > > However, when "ti,pwron-active-high" is absent, its status could > > > have been set previously by a bootloader or by a previous running > > > kernel. =20 > > > > or by EEPROM. > > > > Do they bother to put the chip in a wrong, non-default state at > > boot? =20 >=20 > I was working on a hardware bring-up with the TUSB7320, and I never > saw it happen. That could practically only happen due to a bug. Seems more likely that EEPROM or boot FW may set the bit because it's required by the board and then the kernel could clear it for lack of knowledge. If there is ever a need to support clearing the bit, it would better be done by checking if the DT property is specified at all, and only then tweaking the bit accordingly. Otherwise, leave it alone. Regards, Michal