From: "Chang S. Bae" <chang.seok.bae@intel.com>
To: linux-kernel@vger.kernel.org
Cc: x86@kernel.org, tglx@kernel.org, mingo@redhat.com, bp@alien8.de,
dave.hansen@linux.intel.com, kevin.shu@intel.com,
chang.seok.bae@intel.com
Subject: [PATCH RFC v1 2/8] x86/hotplug: Implement SMT-primary selection for parallel bringup
Date: Sat, 12 Sep 2026 00:08:08 +0000 [thread overview]
Message-ID: <20260912000815.997720-3-chang.seok.bae@intel.com> (raw)
In-Reply-To: <20260912000815.997720-1-chang.seok.bae@intel.com>
Parallel CPU bringup executes in two phases to avoid microcode loading
races between SMT siblings. The core code now supports architecture-
specific customization of the first bringup phase. Implement the x86 logic
to preserve the existing behavior.
Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com>
---
Note:
With this change, the generic SMT-aware two-phase parallel bringup logic
appears redundant since it was originally introduced for the x86
microcode loader path.
But, another architecture, MIPS, also adopted the primary-aware parallel
bringup model in:
76c43eb507bc ("MIPS: SMP: Implement parallel CPU bring up for EyeQ")
So the generic fallback path still appears to have valid users.
---
arch/x86/Kconfig | 1 +
arch/x86/kernel/cpu/microcode/core.c | 18 ++++++++++++++++++
2 files changed, 19 insertions(+)
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 15fd9ec5ecac..cd6d4dfe3349 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -1319,6 +1319,7 @@ config MICROCODE
def_bool y
depends on CPU_SUP_AMD || CPU_SUP_INTEL
select CRYPTO_LIB_SHA256 if CPU_SUP_AMD
+ select HOTPLUG_PARALLEL_ARCH_PRIMARY if HOTPLUG_PARALLEL
config MICROCODE_INITRD32
def_bool y
diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/microcode/core.c
index 0dd0c7241c57..36f08e2c99fb 100644
--- a/arch/x86/kernel/cpu/microcode/core.c
+++ b/arch/x86/kernel/cpu/microcode/core.c
@@ -869,6 +869,24 @@ static int mc_cpu_down_prep(unsigned int cpu)
return 0;
}
+#ifdef CONFIG_HOTPLUG_PARALLEL_ARCH_PRIMARY
+
+/*
+ * Queried by the parallel bringup code to determine whether x86 provides a
+ * custom primary CPU mask for early loading.
+ */
+bool __init arch_cpuhp_primary_aware(void)
+{
+ return __max_threads_per_core > 1;
+}
+
+const struct cpumask *__init arch_cpuhp_get_primary_cpus(void)
+{
+ return cpu_primary_thread_mask;
+}
+
+#endif /* CONFIG_HOTPLUG_PARALLEL_ARCH_PRIMARY */
+
static struct attribute *cpu_root_microcode_attrs[] = {
#ifdef CONFIG_MICROCODE_LATE_LOADING
&dev_attr_reload.attr,
--
2.53.0
next prev parent reply other threads:[~2026-09-12 0:35 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-12 0:08 [PATCH RFC v1 0/8] x86/microcode: Enable uniform feature Chang S. Bae
2026-09-12 0:08 ` [PATCH RFC v1 1/8] cpu/hotplug: Allow architecture-specific primary CPU bringup Chang S. Bae
2026-09-12 0:08 ` Chang S. Bae [this message]
2026-09-12 0:08 ` [PATCH RFC v1 3/8] x86/cpu/topology: Introduce primary core mask Chang S. Bae
2026-09-12 0:08 ` [PATCH RFC v1 4/8] x86/microcode: Extend struct microcode_ops for uniform loading Chang S. Bae
2026-09-12 0:08 ` [PATCH RFC v1 5/8] x86/microcode: Clarify online enforcement with " Chang S. Bae
2026-09-12 0:08 ` [PATCH RFC v1 6/8] x86/microcode: Support uniform scope for late loading Chang S. Bae
2026-09-12 0:08 ` [PATCH RFC v1 7/8] x86/microcode/intel: Support uniform scope for early loading Chang S. Bae
2026-09-12 0:08 ` [PATCH RFC v1 8/8] x86/microcode/intel: Enable uniform loading Chang S. Bae
2026-09-16 0:45 ` [PATCH RFC v1 0/8] x86/microcode: Enable uniform feature Borislav Petkov
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