[PATCH v4 04/17] gpu: nova-core: add the GIN CPU interrupt tree and MSI EOI registers

[John Hubbard <jhubbard@nvidia.com>]

GIN is the GPU's interrupt controller. It latches each interrupt source
in a two-level tree of LEAF registers summarized by TOP, and raises the
PCI interrupt when an enabled vector in an enabled subtree becomes
pending. A message-signaled interrupt is delivered once per edge, and
pre-Hopper MSI rearms delivery by writing the end-of-interrupt register
in the BAR0 mirror of PCI configuration space.

Add the CPU tree registers that receiving GSP interrupts and running the
software-triggered self-test need: the leaf pending and enable arrays,
the TOP enables, and the leaf trigger. Add the end-of-interrupt
register, NV_XVE_CYA_2, alongside them.

Use the NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_* names on every part. The
pre-Hopper headers call the same tree NV_CTRL, but each function reaches
its own tree through this aperture on both families. Declare the leaf
arrays at 16 entries, the widest tree any supported part implements.
Later patches bound every access by the part's leaf count.

Leave the read-only TOP summary undeclared. A vector that latched while
disabled does not appear in TOP, so nova-core never descends from it and
reads every implemented leaf instead.

Declare each leaf field as a set of vectors within one leaf and each TOP
field as a set of subtrees, so a set of subtrees cannot be written to a
leaf register, nor the reverse. The trigger register's vector field is
12 bits wide, wider than any GIN vector, so a vector converts into it
infallibly.

Assisted-by: LLM
Reviewed-by: Will Pierce <wpierce@nvidia.com>
Signed-off-by: John Hubbard <jhubbard@nvidia.com>
---
 drivers/gpu/nova-core/irq.rs                |  1 +
 drivers/gpu/nova-core/irq/interrupt_tree.rs | 14 ++++
 drivers/gpu/nova-core/irq/regs.rs           | 87 +++++++++++++++++++++
 3 files changed, 102 insertions(+)
 create mode 100644 drivers/gpu/nova-core/irq/regs.rs

diff --git a/drivers/gpu/nova-core/irq.rs b/drivers/gpu/nova-core/irq.rs
index f1323f633a03..1ec0bb055d3b 100644
--- a/drivers/gpu/nova-core/irq.rs
+++ b/drivers/gpu/nova-core/irq.rs
@@ -10,3 +10,4 @@
 //! See `Documentation/gpu/nova/core/interrupts.rst`.
 
 mod interrupt_tree;
+mod regs;
diff --git a/drivers/gpu/nova-core/irq/interrupt_tree.rs b/drivers/gpu/nova-core/irq/interrupt_tree.rs
index 24976a3146be..5c7829ea3bc5 100644
--- a/drivers/gpu/nova-core/irq/interrupt_tree.rs
+++ b/drivers/gpu/nova-core/irq/interrupt_tree.rs
@@ -16,6 +16,8 @@
 
 use crate::num;
 
+use super::regs::*;
+
 /// Number of vectors one leaf register carries, one per bit.
 const VECTORS_PER_LEAF: u32 = u32::BITS;
 
@@ -31,6 +33,12 @@
 /// Number of bits needed to address every vector in the widest supported tree.
 const VECTOR_BITS: u32 = (MAX_NUM_LEAVES * VECTORS_PER_LEAF).ilog2();
 
+/// Width of the vector field in the leaf trigger register.
+const TRIGGER_VECTOR_BITS: u32 = {
+    let range = NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_TRIGGER::VECTOR_RANGE;
+    num::u8_as_u32(*range.end() - *range.start() + 1)
+};
+
 /// Index of a leaf register within the widest supported tree. An 8-leaf tree implements only the
 /// lower half of the range.
 pub(super) type LeafIndex = Bounded<usize, { MAX_NUM_LEAVES.ilog2() }>;
@@ -236,3 +244,9 @@ pub(super) const fn validate(self, leaves: LeafCount) -> Result {
         Ok(())
     }
 }
+
+impl From<GinVector> for Bounded<u32, TRIGGER_VECTOR_BITS> {
+    fn from(vector: GinVector) -> Self {
+        vector.0.extend()
+    }
+}
diff --git a/drivers/gpu/nova-core/irq/regs.rs b/drivers/gpu/nova-core/irq/regs.rs
new file mode 100644
index 000000000000..eef28425a74a
--- /dev/null
+++ b/drivers/gpu/nova-core/irq/regs.rs
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0
+// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+
+use kernel::io::register;
+
+use crate::driver::NovaRegisters;
+
+use super::interrupt_tree::{
+    LeafMask,
+    SubtreeSet, //
+};
+
+// The GIN CPU interrupt tree, reached through the `NV_VIRTUAL_FUNCTION_PRIV` aperture. See
+// "Register naming" in `Documentation/gpu/nova/core/interrupts.rst`. The leaf arrays are declared
+// with 16 entries, the widest tree any supported part implements.
+
+register! {
+    base: NovaRegisters;
+
+    /// Pending bits of one leaf, one per vector.
+    ///
+    /// Vector `v` is bit `v % 32` of leaf `v / 32`. The bit is set when the vector's source
+    /// drives it, whether or not the vector is enabled. Writing a `1` clears the bit, and a `0`
+    /// leaves it as it was.
+    pub(super) NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF(u32)[16] @ 0x00b81000 {
+        /// The vectors pending in this leaf.
+        31:0    vectors => LeafMask;
+    }
+
+    /// Enables vectors of one leaf.
+    ///
+    /// A `1` enables the matching vector, and a `0` leaves it as it was.
+    pub(super) NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET(u32)[16] @ 0x00b81200 {
+        /// Vectors to enable.
+        31:0    vectors => LeafMask;
+    }
+
+    /// Disables vectors of one leaf.
+    ///
+    /// A `1` disables the matching vector, and a `0` leaves it as it was. A disabled vector still
+    /// latches in `LEAF`, and `TOP` does not show it.
+    pub(super) NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR(u32)[16] @ 0x00b81400 {
+        /// Vectors to disable.
+        31:0    vectors => LeafMask;
+    }
+
+    /// Enables subtrees.
+    ///
+    /// Bit `N` covers subtree `N`, which is leaves `2N` and `2N + 1`. A `1` enables the matching
+    /// subtree, and a `0` leaves it as it was.
+    ///
+    /// The hardware headers declare a one-element array, so nova-core declares a scalar.
+    pub(super) NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET(u32) @ 0x00b81608 {
+        /// Subtrees to enable.
+        31:0    subtrees => SubtreeSet;
+    }
+
+    /// Disables subtrees, with the bit layout of `TOP_EN_SET`.
+    ///
+    /// A `1` disables the matching subtree, and a `0` leaves it as it was. A disabled subtree
+    /// delivers nothing, and `TOP` still reports it.
+    pub(super) NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR(u32) @ 0x00b81610 {
+        /// Subtrees to disable.
+        31:0    subtrees => SubtreeSet;
+    }
+
+    /// Latches a vector from software. Write-only.
+    ///
+    /// The written vector latches in its `LEAF` register as its own source would, and reaches the
+    /// CPU under the same enables. Implemented on every supported part.
+    pub(super) NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_TRIGGER(u32) @ 0x00b81640 {
+        /// Vector to latch.
+        11:0    vector;
+    }
+}
+
+// PCI configuration-space mirror in BAR0.
+
+register! {
+    base: NovaRegisters;
+
+    /// MSI end-of-interrupt register. Writing any value rearms MSI delivery.
+    ///
+    /// Only pre-Hopper MSI rearms through this register. See "Rearming PCI interrupt delivery"
+    /// in `Documentation/gpu/nova/core/interrupts.rst`.
+    pub(super) NV_XVE_CYA_2(u32) @ 0x00088704 {}
+}
-- 
2.55.0