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Sat, 12 Sep 2026 18:36:22 -0700 (PDT) Received: from localhost.localdomain ([104.39.73.78]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-530f6823ba5sm13156941cf.28.2026.09.12.18.36.20 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 12 Sep 2026 18:36:20 -0700 (PDT) From: Myeonghun Pak To: Andy Shevchenko , Lee Jones Cc: mfd@lists.linux.dev, linux-kernel@vger.kernel.org, Myeonghun Pak , Ijae Kim Subject: [PATCH] mfd: intel_soc_pmic_crc: balance IRQ wake enable Date: Sat, 12 Sep 2026 21:36:15 -0400 Message-ID: <20260913013615.22615-1-mhun512@gmail.com> X-Mailer: git-send-email 2.47.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The INT33FD Crystal Cove driver enables the parent IRQ as a wake source after registering its regmap IRQ chip. When that succeeds, a later mfd_add_devices() failure or driver removal leaves the wake enable unbalanced. Register a managed action only after enable_irq_wake() succeeds. Since the action is registered after the managed regmap IRQ chip, reverse devres order disables IRQ wake before tearing down the IRQ chip. Keep warning and continuing when enable_irq_wake() itself fails. This is limited to the Bay Trail and Cherry Trail Crystal Cove PMIC variants using the INT33FD ACPI ID. This issue was identified during our ongoing static-analysis research while reviewing kernel code. Fixes: 516523846006 ("mfd: intel_soc_pmic: Core driver") Assisted-by: OpenAI:GPT-5.6 Co-developed-by: Ijae Kim Signed-off-by: Ijae Kim Signed-off-by: Myeonghun Pak --- drivers/mfd/intel_soc_pmic_crc.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/mfd/intel_soc_pmic_crc.c b/drivers/mfd/intel_soc_pmic_crc.c index 627a89334..963dde430 100644 --- a/drivers/mfd/intel_soc_pmic_crc.c +++ b/drivers/mfd/intel_soc_pmic_crc.c @@ -164,6 +164,13 @@ static const struct crystal_cove_config crystal_cove_config_cht_crc = { .irq_chip = &crystal_cove_irq_chip, }; +static void crystal_cove_disable_irq_wake(void *data) +{ + struct intel_soc_pmic *pmic = data; + + disable_irq_wake(pmic->irq); +} + static int crystal_cove_i2c_probe(struct i2c_client *i2c) { const struct crystal_cove_config *config; @@ -195,8 +202,14 @@ static int crystal_cove_i2c_probe(struct i2c_client *i2c) return ret; ret = enable_irq_wake(pmic->irq); - if (ret) + if (ret) { dev_warn(dev, "Can't enable IRQ as wake source: %d\n", ret); + } else { + ret = devm_add_action_or_reset(dev, + crystal_cove_disable_irq_wake, pmic); + if (ret) + return ret; + } /* Add lookup table for crc-pwm */ pwm_add_table(crc_pwm_lookup, ARRAY_SIZE(crc_pwm_lookup)); -- 2.47.1