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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-39d98e60484sm19488728a91.4.2026.09.14.02.40.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Sep 2026 02:40:57 -0700 (PDT) From: Yin Li Date: Mon, 14 Sep 2026 17:37:58 +0800 Subject: [PATCH DNM RFC v2 10/10] arm64: dts: qcom: kaanapali: Add MPAM MSC nodes for the L2 caches Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260914-mpam-resctrl-dt-knp-support-v2-10-bf6645bb2f65@oss.qualcomm.com> References: <20260914-mpam-resctrl-dt-knp-support-v2-0-bf6645bb2f65@oss.qualcomm.com> In-Reply-To: <20260914-mpam-resctrl-dt-knp-support-v2-0-bf6645bb2f65@oss.qualcomm.com> To: James Morse , Rob Herring , Shanker Donthineni , Ben Horgan , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Greg Kroah-Hartman , "Rafael J. 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Each MSC is nested directly under its L2 cache node so that the cache node is the MSC's parent device and its CPU affinity is derived from that cache. The L2 cache nodes are placed directly under the root node. The root is the root of the physical address space, so each cache node only needs an identity 'ranges' property for its nested MSC's 'reg' to be resolved to a physical address. The two caches use distinct node names (l2-cache-0 and l2-cache-1) since a cache node has no MMIO unit-address of its own. The nodes are disabled by default. Production firmware does not expose MSC register access to the OS, so these nodes can only be enabled on a local test setup where firmware permits direct MMIO access to the MSCs. This DTS is therefore only an example for other platform DT authors and is not intended to be merged. Co-developed-by: Huang Yiwei Signed-off-by: Huang Yiwei Signed-off-by: Yin Li --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 50 +++++++++++++++++++++++++-------- 1 file changed, 38 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi index 131fd2a16c54..b1dcb1e9c570 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -48,12 +48,6 @@ cpu0: cpu@0 { power-domains = <&cpu_pd0>, <&scmi_perf 0>; power-domain-names = "psci", "perf"; #cooling-cells = <2>; - - l2_0: l2-cache { - compatible = "cache"; - cache-level = <2>; - cache-unified; - }; }; cpu1: cpu@100 { @@ -120,12 +114,6 @@ cpu6: cpu@10000 { power-domains = <&cpu_pd6>, <&scmi_perf 1>; power-domain-names = "psci", "perf"; #cooling-cells = <2>; - - l2_1: l2-cache { - compatible = "cache"; - cache-level = <2>; - cache-unified; - }; }; cpu7: cpu@10100 { @@ -531,6 +519,44 @@ soccp_smp2p_in: slave-kernel { }; }; + l2_0: l2-cache-0 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0xc00000>; + ranges; + + #address-cells = <2>; + #size-cells = <2>; + + msc@19870000 { + compatible = "arm,mpam-msc"; + reg = <0x0 0x19870000 0x0 0x10000>; + arm,not-ready-us = <1>; + status = "disabled"; + }; + + }; + + l2_1: l2-cache-1 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0xc00000>; + ranges; + + #address-cells = <2>; + #size-cells = <2>; + + msc@1a870000 { + compatible = "arm,mpam-msc"; + reg = <0x0 0x1a870000 0x0 0x10000>; + arm,not-ready-us = <1>; + status = "disabled"; + }; + + }; + soc: soc@0 { compatible = "simple-bus"; -- 2.34.1