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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-39d98e60484sm19488728a91.4.2026.09.14.02.40.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Sep 2026 02:40:25 -0700 (PDT) From: Yin Li Date: Mon, 14 Sep 2026 17:37:54 +0800 Subject: [PATCH RFC v2 06/10] arm_mpam: Add support for memory controller MSC on DT platforms Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260914-mpam-resctrl-dt-knp-support-v2-6-bf6645bb2f65@oss.qualcomm.com> References: <20260914-mpam-resctrl-dt-knp-support-v2-0-bf6645bb2f65@oss.qualcomm.com> In-Reply-To: <20260914-mpam-resctrl-dt-knp-support-v2-0-bf6645bb2f65@oss.qualcomm.com> To: James Morse , Rob Herring , Shanker Donthineni , Ben Horgan , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Greg Kroah-Hartman , "Rafael J. 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Memory-controller MSCs cannot be probed yet. Add support to discover memory-controller MSCs from the device tree: derive the component id from the NUMA node and create a 'memory' class RIS, and treat a memory parent as accessible from all CPUs. Signed-off-by: Shanker Donthineni [ morse: split out of a bigger patch, added affinity piece ] Signed-off-by: James Morse [ Yin Li: fix context offset conflicts; use of_node_get() for the memory parent to avoid a refcount underflow; use u32 instead of unsigned long for component_id and compare against ~0U ] Signed-off-by: Yin Li --- drivers/resctrl/mpam_devices.c | 55 ++++++++++++++++++++++++++++++------------ 1 file changed, 40 insertions(+), 15 deletions(-) diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c index 7a5b27e87759..480e38cfa86d 100644 --- a/drivers/resctrl/mpam_devices.c +++ b/drivers/resctrl/mpam_devices.c @@ -263,10 +263,12 @@ static int mpam_dt_parse_resource(struct mpam_msc *msc, struct device_node *np, u8 ris_idx) { int err = 0; - u32 level = 0; - u32 cache_id; + u32 class_id = 0; + u32 component_id = 0; struct device *dev = &msc->pdev->dev; + enum mpam_class_types type = MPAM_CLASS_UNKNOWN; struct device_node *cache __free(device_node) = NULL; + struct device_node *memory __free(device_node) = NULL; struct device_node *parent __free(device_node) = of_get_parent(np); if (of_device_is_compatible(np, "arm,mpam-cache")) { @@ -275,27 +277,48 @@ static int mpam_dt_parse_resource(struct mpam_msc *msc, struct device_node *np, dev_err_once(dev, "Failed to read phandle\n"); return -EINVAL; } + type = MPAM_CLASS_CACHE; + } else if (of_device_is_compatible(parent, "cache")) { cache = of_node_get(parent); + type = MPAM_CLASS_CACHE; + } else if (of_device_is_compatible(np, "arm,mpam-memory")) { + memory = of_parse_phandle(np, "arm,mpam-device", 0); + if (!memory) { + dev_err_once(dev, "Failed to read phandle\n"); + return -EINVAL; + } + type = MPAM_CLASS_MEMORY; + } else if (of_device_is_compatible(np, "arm,mpam-memory-controller-msc")) { + memory = of_node_get(parent); + type = MPAM_CLASS_MEMORY; } else { - /* For now, only caches are supported */ - cache = NULL; - return err; - } - - err = of_property_read_u32(cache, "cache-level", &level); - if (err) { - dev_err_once(dev, "Failed to read cache-level\n"); + /* + * For now, only caches and memory controllers are + * supported. + */ return err; } - cache_id = cache_of_calculate_id(cache); - if (cache_id == ~0U) { - dev_err_once(dev, "Failed to calculate cache-id\n"); - return -ENOENT; + /* Determine the class and component ids, based on type. */ + if (type == MPAM_CLASS_CACHE) { + err = of_property_read_u32(cache, "cache-level", &class_id); + if (err) { + dev_err_once(dev, "Failed to read cache-level\n"); + return err; + } + component_id = cache_of_calculate_id(cache); + if (component_id == ~0U) { + dev_err_once(dev, "Failed to calculate cache-id\n"); + return -ENOENT; + } + } else if (type == MPAM_CLASS_MEMORY) { + err = of_node_to_nid(np); + component_id = (err == NUMA_NO_NODE) ? 0 : err; + class_id = MPAM_CLASS_ID_DEFAULT; } - return mpam_ris_create(msc, ris_idx, MPAM_CLASS_CACHE, level, cache_id); + return mpam_ris_create(msc, ris_idx, type, class_id, component_id); } static int mpam_dt_parse_resources(struct mpam_msc *msc, void *ignored) @@ -2169,6 +2192,8 @@ static void update_msc_accessibility(struct mpam_msc *msc) } else { if (of_device_is_compatible(parent, "cache")) get_cpumask_from_cache(parent, &msc->accessibility); + else if (of_device_is_compatible(parent, "memory")) + cpumask_copy(&msc->accessibility, cpu_possible_mask); else dev_err_once(dev, "Cannot determine accessibility of MSC.\n"); } -- 2.34.1