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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-39d98e60484sm19488728a91.4.2026.09.14.02.40.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Sep 2026 02:40:49 -0700 (PDT) From: Yin Li Date: Mon, 14 Sep 2026 17:37:57 +0800 Subject: [PATCH RFC v2 09/10] arm_mpam: Support MSC accessibility derivation from RIS nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260914-mpam-resctrl-dt-knp-support-v2-9-bf6645bb2f65@oss.qualcomm.com> References: <20260914-mpam-resctrl-dt-knp-support-v2-0-bf6645bb2f65@oss.qualcomm.com> In-Reply-To: <20260914-mpam-resctrl-dt-knp-support-v2-0-bf6645bb2f65@oss.qualcomm.com> To: James Morse , Rob Herring , Shanker Donthineni , Ben Horgan , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Greg Kroah-Hartman , "Rafael J. Wysocki" , Danilo Krummrich , Reinette Chatre , Fenghua Yu , Jonathan Cameron , Bjorn Andersson , Konrad Dybcio , Gavin Shan Cc: Yin Li , Andre Przywara , Drew Fustini , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Shaopeng Tan , trilok.soni@oss.qualcomm.com, aiqun.yu@oss.qualcomm.com, ganapatrao.kulkarni@oss.qualcomm.com, Srivathsa L Rao , Huang Yiwei , linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, driver-core@lists.linux.dev, devicetree@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789378767; l=6269; i=yin.li@oss.qualcomm.com; s=20260811; h=from:subject:message-id; bh=6aXcuNFRRTDlvGN+TsA+86KnLS6uQ6WRYT0BfzhuKws=; b=bBQpLcPvbQkOwg42mxykFwgzeNMrLYkvmlHOl2AGfilHAAgu7ACzGrPmI6ia6F5ZPYIR2VX4z GvQ3J7nPV2uDZDl8IQxmBFkTY+MyPGCT0D/Ot5op5knchONGKHD6MT7 X-Developer-Key: i=yin.li@oss.qualcomm.com; a=ed25519; pk=e/2LM97aSWGBMrxY240URBi9Zi8/kL5hXgB+VHkYvW0= X-Proofpoint-ORIG-GUID: gQBdQ4NXD-atXyGgZRTCQCmStpb4cSJs X-Proofpoint-Spam-Info: AW1haW4tMjYwOTE0MDEzNyBTYWx0ZWRfX/lW7eBjfn8KE 0OEvw8g5i/6ZWIqnRwahr8EoBCA0xtB9WFzGoMTuBImiNRuxKJH7vNE70Pp9X6ICmQ8jBAbnloK Jh9Maf6VKOpwQovnFWhi+CofqBeIMp8= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTE0MDEzNyBTYWx0ZWRfX3/uwMe01Wtwn f+oR7IknwaJ8GDqi5LQL2x1d+LW08PAksA4QWKDekLtsC6XlvLLYtqkUjU00kmKO4EHLxs3oQoj np6f4TdmhYttJw6Rd11Xae/x0Iq3jMEle4YORDluGNrMluuK8MNwJbTgAcLkguKOI5/qPRIEsR8 yj+UBP5TeO/N83JCMdz8NCAycQdq5tBFLLgZPIwM2jtRAbIZYJqu3ru9JinNEfAWF2S++hl7lru Xb+n7RCvHG42DiXE5VGQQC0uZy1McX2HiaXutROYbiy5dYPukU1NmENXdCGF0ZoI45a7NVsF/0G DfVjjJRtHtqY5bViCOIVVoxPPxMo9j6QjdYXhfT9J8HCPjsvcQbQKHoGW/oXjcP3jEIjUh8Yi5m 778bRNmMwBr7HKB/DbZ9QrGDOrLlK0Ll764hwMGboWshPTvHixbPpcTmddo1a1q4Rv98j0FQzGs yuDI+scSoMs8k/BgP5A== X-Authority-Analysis: v=2.4 cv=XKel2ghE c=1 sm=1 tr=0 ts=6aa7c123 cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=DmVZOekaPyhSFRrspXcA:9 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-GUID: gQBdQ4NXD-atXyGgZRTCQCmStpb4cSJs X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-14_02,2026-09-13_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 adultscore=0 spamscore=0 bulkscore=0 phishscore=0 priorityscore=1501 impostorscore=0 malwarescore=0 clxscore=1015 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609140137 The DT accessibility derivation only handled MSCs whose parent node is a cache or memory device. When the MSC is placed under a generic container (e.g. directly under /soc), the parent gives no affinity hint and there is no fallback. Add a per-RIS fallback path for when the parent node is not a recognised cache or memory device. For each available RIS child node, affinity is resolved in two steps: first from an explicit 'cpus' phandle-array on the RIS node, then from the 'arm,mpam-device' phandle. The final accessibility mask is the union of all RIS masks; if any RIS fails to resolve, the mask is cleared and the MSC fails to probe rather than come up with a partial affinity. Factor the DT-specific logic into mpam_dt_update_msc_accessibility() so that update_msc_accessibility() dispatches cleanly between ACPI and DT paths. Co-developed-by: Huang Yiwei Signed-off-by: Huang Yiwei Signed-off-by: Yin Li --- drivers/resctrl/mpam_devices.c | 146 ++++++++++++++++++++++++++++++++++++----- 1 file changed, 131 insertions(+), 15 deletions(-) diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c index 7ef3ed55b066..ede1b157ab57 100644 --- a/drivers/resctrl/mpam_devices.c +++ b/drivers/resctrl/mpam_devices.c @@ -2159,6 +2159,136 @@ static int mpam_msc_setup_error_irq(struct mpam_msc *msc) return 0; } +/* + * Resolve a RIS to its CPU affinity from its 'cpus' phandle-array. + * Returns -ENODEV when 'cpus' is absent (the caller may use another source), + * -EINVAL when any phandle is invalid, or 0 on full success. + */ +static int get_cpumask_from_ris_cpus(struct device_node *ris_np, + cpumask_t *affinity) +{ + int i, cpu_phandle_count; + + cpu_phandle_count = of_count_phandle_with_args(ris_np, "cpus", NULL); + if (cpu_phandle_count <= 0) + return -ENODEV; + + for (i = 0; i < cpu_phandle_count; i++) { + struct device_node *phandle_np __free(device_node) = + of_parse_phandle(ris_np, "cpus", i); + int cpu, matched = -1; + + if (phandle_np) { + for_each_possible_cpu(cpu) { + struct device_node *cpu_node __free(device_node) = + of_get_cpu_node(cpu, NULL); + + if (phandle_np == cpu_node) { + matched = cpu; + break; + } + } + } + + if (matched < 0) { + pr_warn("MPAM: RIS %pOF cpus[%d] (%pOF) is not a possible CPU\n", + ris_np, i, phandle_np); + return -EINVAL; + } + + cpumask_set_cpu(matched, affinity); + } + + return 0; +} + +/* + * Resolve a RIS to its CPU affinity from its 'arm,mpam-device' phandle. + * Returns -EINVAL when 'arm,mpam-device' is absent or the phandle is invalid. + * 0 on full success. + */ +static int get_cpumask_from_ris_phandle(struct device_node *ris, + cpumask_t *affinity) +{ + struct device_node *mpam_device __free(device_node) = + of_parse_phandle(ris, "arm,mpam-device", 0); + + if (!mpam_device) { + pr_warn("MPAM: RIS %pOF has neither 'cpus' nor 'arm,mpam-device'\n", + ris); + return -EINVAL; + } + + if (of_device_is_compatible(mpam_device, "cache")) + return get_cpumask_from_cache(mpam_device, affinity); + + if (of_device_is_compatible(mpam_device, "memory")) { + cpumask_or(affinity, affinity, cpu_possible_mask); + return 0; + } + + return -EINVAL; +} + +static int get_cpumask_from_ris(struct device_node *ris, cpumask_t *affinity) +{ + int err; + + err = get_cpumask_from_ris_cpus(ris, affinity); + if (err != -ENODEV) + return err; + + return get_cpumask_from_ris_phandle(ris, affinity); +} + +/* + * Returns -ENODEV when the parent is just a container (not a recognised device), + * so the caller falls back to the per-RIS description. + */ +static int get_cpumask_from_parent(struct mpam_msc *msc, cpumask_t *affinity) +{ + struct device_node *parent __free(device_node) = + of_get_parent(msc->pdev->dev.of_node); + + if (parent == of_root) { + cpumask_copy(affinity, cpu_possible_mask); + return 0; + } + + if (of_device_is_compatible(parent, "cache")) + return get_cpumask_from_cache(parent, affinity); + + if (of_device_is_compatible(parent, "memory")) { + cpumask_copy(affinity, cpu_possible_mask); + return 0; + } + + return -ENODEV; +} + +/* + * An MSC's CPU affinity is described either by its parent node or, when the + * parent is just a container, per-RIS inside the MSC. In the per-RIS case the + * accessibility is the union of the RIS affinities: every RIS must resolve, so + * a single failure clears the mask and stops and the MSC fails to probe rather + * than come up with a partial affinity. + */ +static void mpam_dt_update_msc_accessibility(struct mpam_msc *msc) +{ + cpumask_t *affinity = &msc->accessibility; + + cpumask_clear(affinity); + + if (get_cpumask_from_parent(msc, affinity) == -ENODEV) { + for_each_available_child_of_node_scoped(msc->pdev->dev.of_node, ris) { + if (get_cpumask_from_ris(ris, affinity)) { + cpumask_clear(affinity); + break; + } + } + } +} + /* * An MSC can control traffic from a set of CPUs, but may only be accessible * from a (hopefully wider) set of CPUs. The common reason for this is power @@ -2168,8 +2298,6 @@ static int mpam_msc_setup_error_irq(struct mpam_msc *msc) */ static void update_msc_accessibility(struct mpam_msc *msc) { - struct device *dev = &msc->pdev->dev; - struct device_node *parent; u32 affinity_id; int err; @@ -2185,19 +2313,7 @@ static void update_msc_accessibility(struct mpam_msc *msc) return; } - /* Where an MSC can be accessed from depends on the path to of_node. */ - parent = of_get_parent(msc->pdev->dev.of_node); - if (parent == of_root) { - cpumask_copy(&msc->accessibility, cpu_possible_mask); - } else { - if (of_device_is_compatible(parent, "cache")) - get_cpumask_from_cache(parent, &msc->accessibility); - else if (of_device_is_compatible(parent, "memory")) - cpumask_copy(&msc->accessibility, cpu_possible_mask); - else - dev_err_once(dev, "Cannot determine accessibility of MSC.\n"); - } - of_node_put(parent); + mpam_dt_update_msc_accessibility(msc); } /* -- 2.34.1