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Mon, 14 Sep 2026 00:52:39 -0700 From: Zhi Wang To: , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Zhi Wang Subject: [PATCH v2 25/32] gpu: nova-core: vgpu: initialize GSP plugin RPC buffers Date: Mon, 14 Sep 2026 10:49:00 +0300 Message-ID: <20260914074907.1399629-26-zhiw@nvidia.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260914074907.1399629-1-zhiw@nvidia.com> References: <20260914074907.1399629-1-zhiw@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF0000A894:EE_|CY8PR12MB7316:EE_ X-MS-Office365-Filtering-Correlation-Id: 2497d26c-0812-4fc8-0bd6-08df123537ca X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700016|376014|7416014|1800799024|23010399003|56012099006|6133799003|11063799006|3023799007|22082099003|10067099003|18002099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: HQc7AV1PS/M8fuhtuk1EtgZKpH52EXvkYTA4IfD5uHGpmlosja55OMUrZ5NiJAXI/fq5b5bBf22BFyuAQ0NJldwHbBFZta8HJgnVxqu5x1h5UG7JkTJPWE6GSbUUvbTNYTsaeIR2DtREWEUwbZiomCb4FvIyhUnbw9mDoyY3tBZDrBAXwPf7xyaNAV6+U4Ex8zm72wxY3B65auTnWQ8k+YWXyd6/qj5cMulFwY7RiL6VOeMkmyaYMRhr96KNDArh1hJPoQ9VGkZ2bExpEToPjQprgvylBvWF/vekWtdhMOULJkm3I8Y8lFk5FMU3bAWng963Yl52Eiw42NQRCeWTro8V5EpljpLicds+CJRZTOqWNS9aPVWcqcFdwQbdCvajYnSC2SqOIT7qYRaAKO3RCmlO7Nzut7KZ2hkkHPrLhV+a4sTpTj8u8ThYx7UVUgeq X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Sep 2026 07:53:08.6673 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2497d26c-0812-4fc8-0bd6-08df123537ca X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF0000A894.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7316 After the GSP plugin has been successfully booted, the vGPU manager uses the GSP plugin RPC interface to communicate with it through a shared RPC buffer. The shared buffer needs region offsets, a protocol version and initial control and response state before the first request. The control sequence field also carries the boot-ready marker, so initialization must follow the plugin's ready indication. Add BAR1 accessors to initialize the shared control and response buffers. Signed-off-by: Zhi Wang --- drivers/gpu/nova-core/mm/bar_user.rs | 10 ++ drivers/gpu/nova-core/vgpu/fw.rs | 2 + drivers/gpu/nova-core/vgpu/gsp_plugin_comm.rs | 142 +++++++++++++++++- 3 files changed, 147 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/nova-core/mm/bar_user.rs b/drivers/gpu/nova-core/mm/bar_user.rs index ef357fd516b7..b7b4bf14b56d 100644 --- a/drivers/gpu/nova-core/mm/bar_user.rs +++ b/drivers/gpu/nova-core/mm/bar_user.rs @@ -141,6 +141,11 @@ pub(crate) fn try_read32(&self, offset: usize) -> Result { self.bar_user.bar1.try_read32(off) } + fn try_write8(&self, value: u8, offset: usize) -> Result { + let off = self.bar_offset(offset)?; + self.bar_user.bar1.try_write8(value, off) + } + /// Write a 32-bit value at the given offset. pub(crate) fn try_write32(&self, value: u32, offset: usize) -> Result { let off = self.bar_offset(offset)?; @@ -261,6 +266,11 @@ pub(crate) fn try_read32(&self, offset: usize) -> Result { .try_read32(self.access_offset(offset, size_of::())?) } + pub(crate) fn try_write8(&self, value: u8, offset: usize) -> Result { + self.access + .try_write8(value, self.access_offset(offset, size_of::())?) + } + pub(crate) fn try_write32(&self, value: u32, offset: usize) -> Result { self.access .try_write32(value, self.access_offset(offset, size_of::())?) diff --git a/drivers/gpu/nova-core/vgpu/fw.rs b/drivers/gpu/nova-core/vgpu/fw.rs index 1528cc56ce74..03225b9833c3 100644 --- a/drivers/gpu/nova-core/vgpu/fw.rs +++ b/drivers/gpu/nova-core/vgpu/fw.rs @@ -15,12 +15,14 @@ VGPU_CPU_GSP_COMMUNICATION_BUFF_TOTAL_SIZE, VGPU_CPU_GSP_CTRL_BUFF_REGION as RawControlRegion, VGPU_CPU_GSP_CTRL_BUFF_REGION_SIZE, + VGPU_CPU_GSP_CTRL_BUFF_VERSION, VGPU_CPU_GSP_ERROR_BUFF_REGION_SIZE, VGPU_CPU_GSP_GUEST_RPC_TRACE_BUFF_REGION_SIZE, VGPU_CPU_GSP_INIT_TASK_LOG_BUFF_REGION_SIZE, VGPU_CPU_GSP_KERNEL_TASK_LOG_BUFF_REGION_SIZE, VGPU_CPU_GSP_MESSAGE_BUFF_REGION_SIZE, VGPU_CPU_GSP_MIGRATION_BUFF_REGION_SIZE, + VGPU_CPU_GSP_RESPONSE_BUFF_REGION as RawResponseRegion, VGPU_CPU_GSP_RESPONSE_BUFF_REGION_SIZE, VGPU_CPU_GSP_VGPU_TASK_LOG_BUFF_REGION_SIZE, // }; diff --git a/drivers/gpu/nova-core/vgpu/gsp_plugin_comm.rs b/drivers/gpu/nova-core/vgpu/gsp_plugin_comm.rs index af7a396021bc..5d129a1b908f 100644 --- a/drivers/gpu/nova-core/vgpu/gsp_plugin_comm.rs +++ b/drivers/gpu/nova-core/vgpu/gsp_plugin_comm.rs @@ -16,7 +16,8 @@ use super::fw::{ self, - RawControlRegion, // + RawControlRegion, + RawResponseRegion, // }; /// Physical VRAM regions containing the vGPU plugin logs. @@ -75,9 +76,14 @@ fn take_region(region: &VramRegion, cursor: &mut u64, size: u32) -> Result { map: BarMapping<'map, 'gpu>, control: VramRegion, + response: VramRegion, + message: VramRegion, + migration: VramRegion, + error: VramRegion, init_log: VramRegion, vgpu_log: VramRegion, kernel_log: VramRegion, + guest_trace: VramRegion, } impl<'map, 'gpu> CommBufferRegion<'map, 'gpu> { @@ -92,22 +98,22 @@ pub(super) fn new( let mut cursor = 0; let control = take_region(®ion, &mut cursor, fw::VGPU_CPU_GSP_CTRL_BUFF_REGION_SIZE)?; - take_region( + let response = take_region( ®ion, &mut cursor, fw::VGPU_CPU_GSP_RESPONSE_BUFF_REGION_SIZE, )?; - take_region( + let message = take_region( ®ion, &mut cursor, fw::VGPU_CPU_GSP_MESSAGE_BUFF_REGION_SIZE, )?; - take_region( + let migration = take_region( ®ion, &mut cursor, fw::VGPU_CPU_GSP_MIGRATION_BUFF_REGION_SIZE, )?; - take_region( + let error = take_region( ®ion, &mut cursor, fw::VGPU_CPU_GSP_ERROR_BUFF_REGION_SIZE, @@ -127,13 +133,16 @@ pub(super) fn new( &mut cursor, fw::VGPU_CPU_GSP_KERNEL_TASK_LOG_BUFF_REGION_SIZE, )?; - take_region( + let guest_trace = take_region( ®ion, &mut cursor, fw::VGPU_CPU_GSP_GUEST_RPC_TRACE_BUFF_REGION_SIZE, )?; - if cursor != total_size || control.size() != u64::try_from(size_of::())? { + if cursor != total_size + || control.size() != u64::try_from(size_of::())? + || response.size() != u64::try_from(size_of::())? + { return Err(EINVAL); } @@ -142,9 +151,14 @@ pub(super) fn new( Ok(Self { map, control, + response, + message, + migration, + error, init_log, vgpu_log, kernel_log, + guest_trace, }) } @@ -176,6 +190,21 @@ fn read_u32(&self, region: &VramRegion, field: usize) -> Result { .try_read32(self.io_offset(region, field, size_of::())?) } + fn write_u8(&self, region: &VramRegion, field: usize, value: u8) -> Result { + self.map + .try_write8(value, self.io_offset(region, field, size_of::())?) + } + + fn write_u32(&self, region: &VramRegion, field: usize, value: u32) -> Result { + self.map + .try_write32(value, self.io_offset(region, field, size_of::())?) + } + + fn write_u64(&self, region: &VramRegion, field: usize, value: u64) -> Result { + self.map + .try_write64(value, self.io_offset(region, field, size_of::())?) + } + /// Return the physical regions occupied by the three plugin logs. pub(super) fn plugin_logs(&self) -> PluginLogRegions { PluginLogRegions { @@ -208,6 +237,105 @@ pub(super) fn is_plugin_ready(&self) -> Result { Ok(value == fw::GSP_PLUGIN_BOOTLOADED) } + /// Initialize the shared control and response buffers for plugin RPC. + #[expect(dead_code)] + pub(super) fn initialize(&self) -> Result { + self.write_u64( + &self.control, + core::mem::offset_of!(RawControlRegion, __bindgen_anon_1.response_buff_offset), + u64::try_from(self.region_offset(&self.response)?)?, + )?; + self.write_u64( + &self.control, + core::mem::offset_of!(RawControlRegion, __bindgen_anon_1.message_buff_offset), + u64::try_from(self.region_offset(&self.message)?)?, + )?; + self.write_u64( + &self.control, + core::mem::offset_of!(RawControlRegion, __bindgen_anon_1.migration_buff_offset), + u64::try_from(self.region_offset(&self.migration)?)?, + )?; + self.write_u64( + &self.control, + core::mem::offset_of!(RawControlRegion, __bindgen_anon_1.error_buff_offset), + u64::try_from(self.region_offset(&self.error)?)?, + )?; + self.write_u64( + &self.control, + core::mem::offset_of!( + RawControlRegion, + __bindgen_anon_1.guest_rpc_trace_buff_offset + ), + u64::try_from(self.region_offset(&self.guest_trace)?)?, + )?; + self.write_u32( + &self.control, + core::mem::offset_of!( + RawControlRegion, + __bindgen_anon_1.migration_buf_cpu_access_offset + ), + 0, + )?; + self.write_u8( + &self.control, + core::mem::offset_of!(RawControlRegion, __bindgen_anon_1.is_migration_in_progress), + 0, + )?; + self.write_u32( + &self.control, + core::mem::offset_of!(RawControlRegion, __bindgen_anon_1.error_buff_cpu_get_idx), + 0, + )?; + self.write_u32( + &self.control, + core::mem::offset_of!( + RawControlRegion, + __bindgen_anon_1.guest_rpc_trace_buff_cpu_get_idx + ), + 0, + )?; + self.write_u32( + &self.control, + core::mem::offset_of!(RawControlRegion, __bindgen_anon_1.attached_vgpu_count), + 1, + )?; + self.write_u8( + &self.control, + core::mem::offset_of!(RawControlRegion, __bindgen_anon_1.is_gr_init_done), + 0, + )?; + + self.write_u32( + &self.control, + core::mem::offset_of!(RawControlRegion, __bindgen_anon_1.message_type), + 0, + )?; + // Replace the boot-ready marker with the initial RPC sequence. + self.write_u32( + &self.control, + core::mem::offset_of!(RawControlRegion, __bindgen_anon_1.message_seq_num), + 0, + )?; + self.write_u32( + &self.response, + core::mem::offset_of!( + RawResponseRegion, + __bindgen_anon_1.message_seq_num_processed + ), + 0, + )?; + self.write_u32( + &self.response, + core::mem::offset_of!(RawResponseRegion, __bindgen_anon_1.result_code), + 0, + )?; + self.write_u32( + &self.control, + core::mem::offset_of!(RawControlRegion, __bindgen_anon_1.version), + fw::VGPU_CPU_GSP_CTRL_BUFF_VERSION, + ) + } + /// Invalidate the PTEs and release the communication mapping. pub(super) fn destroy(self, mm: &mut GpuMm<'_>) -> Result { self.map.destroy(mm)