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Mon, 14 Sep 2026 00:49:46 -0700 From: Zhi Wang To: , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Zhi Wang Subject: [PATCH v2 04/32] gpu: nova-core: gpu: add a channel ID pool for vGPU Date: Mon, 14 Sep 2026 10:48:39 +0300 Message-ID: <20260914074907.1399629-5-zhiw@nvidia.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260914074907.1399629-1-zhiw@nvidia.com> References: <20260914074907.1399629-1-zhiw@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF0000A892:EE_|DM6PR12MB4435:EE_ X-MS-Office365-Filtering-Correlation-Id: 283df39b-fc6f-4a1a-b930-08df1234cbf0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|30052699003|23010399003|36860700016|7416014|376014|1800799024|82310400026|56012099006|11063799006|10067099003|22082099003|18002099003|6133799003; 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The existing allocator is not instantiated by Gpu, leaving no common pool from which consumers can reserve per-VF ranges. The pool must remain at a stable address while its reservations exist. Its storage also needs to remain available throughout GPU cleanup. Create a private pinned ChannelIdPool with a single 2048-channel capacity constant. Initialize it before GSP resources and declare it after them so that it survives both their normal destruction and initialization rollback. No channel reservations are made here. Cc: Alexandre Courbot Suggested-by: Eliot Courtney Signed-off-by: Zhi Wang --- drivers/gpu/nova-core/gpu.rs | 9 +++++++++ drivers/gpu/nova-core/gpu/channel.rs | 4 ++++ 2 files changed, 13 insertions(+) diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs index 39e9e4ab0be6..733a2c09ec01 100644 --- a/drivers/gpu/nova-core/gpu.rs +++ b/drivers/gpu/nova-core/gpu.rs @@ -48,6 +48,7 @@ GpuMm, VramAddress, // }, + num, vgpu::VgpuState, // }; @@ -56,6 +57,10 @@ mod hal; mod regs; +use self::channel::TOTAL_CHANNELS; + +pub(crate) use self::channel::ChannelIdPool; + macro_rules! define_chipset { ({ $($variant:ident = $value:expr),* $(,)* }) => { @@ -322,6 +327,8 @@ pub(crate) struct Gpu<'gpu> { /// GSP and its resources. #[pin] gsp_resources: GspResources<'gpu>, + #[pin] + chid_pool: ChannelIdPool, /// System memory page required for flushing all pending GPU-side memory writes done through /// PCIE into system memory, via sysmembar (A GPU-initiated HW memory-barrier operation). /// @@ -396,6 +403,8 @@ pub(crate) fn new<'a>( // Initialize this early because `gsp_resources` depends on it. sysmem_flush: SysmemFlush::register(dev, bar, spec.chipset)?, + chid_pool <- ChannelIdPool::new(cv!(num::u32_as_usize(TOTAL_CHANNELS))), + gsp_resources <- try_pin_init!(GspResources { device: pdev, diff --git a/drivers/gpu/nova-core/gpu/channel.rs b/drivers/gpu/nova-core/gpu/channel.rs index 485efaba059d..75666c6768e6 100644 --- a/drivers/gpu/nova-core/gpu/channel.rs +++ b/drivers/gpu/nova-core/gpu/channel.rs @@ -21,6 +21,10 @@ }, // }; +// TODO: Query the channel capacity through GMCAPI once an equivalent of +// NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_CHANNELS is available. +pub(super) const TOTAL_CHANNELS: u32 = 2048; + /// Pool for tracking reservations of channel IDs. #[pin_data] pub(crate) struct ChannelIdPool {