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Mon, 14 Sep 2026 00:50:10 -0700 From: Zhi Wang To: , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Zhi Wang Subject: [PATCH v2 07/32] gpu: nova-core: vgpu: initialize runtime parameters after GSP boot Date: Mon, 14 Sep 2026 10:48:42 +0300 Message-ID: <20260914074907.1399629-8-zhiw@nvidia.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260914074907.1399629-1-zhiw@nvidia.com> References: <20260914074907.1399629-1-zhiw@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF0000A890:EE_|DM4PR12MB6040:EE_ X-MS-Office365-Filtering-Correlation-Id: ae390fee-8055-4f81-8ac9-08df1234db80 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|23010399003|376014|1800799024|36860700016|82310400026|7136999003|11063799006|56012099006|6133799003|22082099003|18002099003|11062099010|3023799007|10067099003; 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These resources are only meaningful after a successful vGPU-enabled boot. A disabled GPU should not construct a manager, and a constructed manager should always have its complete runtime parameters. Have Gpu construct an optional VgpuManager from BootResult::static_info after GSP boot. Copy the ordered engine list and VMMU segment size, use the pool's 2048-channel capacity, and store them directly in the manager. Expose read-only accessors tied to the manager, preserving a reported VMMU size of zero. Cc: Alexandre Courbot Signed-off-by: Zhi Wang --- drivers/gpu/nova-core/gpu.rs | 23 ++++++++++++- drivers/gpu/nova-core/gsp/commands.rs | 2 -- drivers/gpu/nova-core/vgpu.rs | 48 ++++++++++++++++++++++++++- 3 files changed, 69 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs index 733a2c09ec01..227531b28541 100644 --- a/drivers/gpu/nova-core/gpu.rs +++ b/drivers/gpu/nova-core/gpu.rs @@ -49,7 +49,10 @@ VramAddress, // }, num, - vgpu::VgpuState, // + vgpu::{ + VgpuManager, + VgpuState, // + }, }; #[cfg_attr(not(CONFIG_KUNIT = "y"), expect(dead_code))] @@ -311,6 +314,7 @@ struct GspResources<'gpu> { #[pin_data] pub(crate) struct Gpu<'gpu> { spec: Spec, + vgpu: Option>, /// GSP event interrupt registration. /// /// Declared before `gsp_resources` so it is dropped first: `free_irq` runs, waiting out any @@ -436,6 +440,23 @@ pub(crate) fn new<'a>( })?, }), + vgpu: { + let info = &gsp_resources.boot_result.static_info; + match gsp_resources.vgpu_state { + VgpuState::Disabled => None, + VgpuState::Enabled { .. } => Some(VgpuManager::new( + // SAFETY: `chid_pool` is initialized above at its final pinned address. + // The private manager and its pool borrow cannot escape this `Gpu`. + // Completed field drop order drops the manager before the pool; on failure, + // pin-init drops it before the earlier-initialized pool. + unsafe { &*core::ptr::from_ref(chid_pool.as_ref().get_ref()) }, + &info.fifo_engine_list, + info.vmmu_segment_size, + TOTAL_CHANNELS, + )), + } + }, + // GSP boot left the SWGEN0 latch set and pending bits in the tree. _: { irq::gsp::quiesce(bar, gsp_resources.spec.chipset, vectors_ref)?; diff --git a/drivers/gpu/nova-core/gsp/commands.rs b/drivers/gpu/nova-core/gsp/commands.rs index 3820320dcb34..c2faa825a849 100644 --- a/drivers/gpu/nova-core/gsp/commands.rs +++ b/drivers/gpu/nova-core/gsp/commands.rs @@ -77,9 +77,7 @@ pub(crate) struct GetGspStaticInfoReply { /// Exclusive end of the FB physical address space. pub(crate) total_fb_end: u64, /// VMMU segment size in bytes, or zero if GSP-RM omitted it. - #[expect(dead_code)] pub(crate) vmmu_segment_size: u64, - #[expect(dead_code)] pub(crate) fifo_engine_list: FifoEngineList, } diff --git a/drivers/gpu/nova-core/vgpu.rs b/drivers/gpu/nova-core/vgpu.rs index b405ba49c490..348af9ea3fc2 100644 --- a/drivers/gpu/nova-core/vgpu.rs +++ b/drivers/gpu/nova-core/vgpu.rs @@ -13,7 +13,11 @@ Fsp, VgpuMode, // }, - gpu::Chipset, // + gpu::{ + ChannelIdPool, + Chipset, // + }, + gsp::commands::FifoEngineList, // }; mod hal; @@ -80,3 +84,45 @@ fn query_state( } } } + +/// Runtime resources for an enabled vGPU boot. +pub(crate) struct VgpuManager<'gpu> { + #[expect(dead_code)] + chid_pool: &'gpu ChannelIdPool, + vmmu_segment_size: u64, + total_channels: u32, + fifo_engine_list: FifoEngineList, +} + +impl<'gpu> VgpuManager<'gpu> { + /// Retains runtime parameters from a completed vGPU-enabled GSP boot. + pub(crate) fn new( + chid_pool: &'gpu ChannelIdPool, + fifo_engine_list: &FifoEngineList, + vmmu_segment_size: u64, + total_channels: u32, + ) -> Self { + Self { + chid_pool, + vmmu_segment_size, + total_channels, + fifo_engine_list: *fifo_engine_list, + } + } + + /// Returns the VMMU segment size in bytes, or zero if GSP-RM omitted it. + #[expect(dead_code)] + const fn vmmu_segment_size(&self) -> u64 { + self.vmmu_segment_size + } + + #[expect(dead_code)] + const fn total_channels(&self) -> u32 { + self.total_channels + } + + #[expect(dead_code)] + fn fifo_engine_list(&self) -> &FifoEngineList { + &self.fifo_engine_list + } +}