From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0D584420482 for ; Mon, 14 Sep 2026 09:39:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789378797; cv=none; b=uBn43CjZxgzKlGW93wWDgFYMpQ61xD2/v892H/GQDcJry+13h9fviBvgoBsZ28zL1IBDiDM5H5bK+8e10yraspEtU/YzwCQZRmvaA2thwEdJFVGmMBUK0sE+s3pFxCLGHCbytdDl3WPzO6S2zVFzG0XJhZNCHS2Ff8AKaprHphQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789378797; c=relaxed/simple; bh=wIVliDo+Smhz04onwGqrzYPtfV9rtmgh95lVsw2Hu4Y=; h=Date:From:To:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=rVwnfVlMHAADlu0PFhu3AERP3yzAoxmI76McSjDI1S4KhX66EtHOP6Y23vrVFZn12qn1f5qRaYFC5v50XoThrxCPt6lUK/LNOPtcVjq6u8mPFRlGCTytOjRYfNqdCO2yBka2AZ9jI28q1raWUFMwgccPnAlsoJ0yUIZ4KqxRmcI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=EhywDeIO; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="EhywDeIO" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1789378793; bh=wIVliDo+Smhz04onwGqrzYPtfV9rtmgh95lVsw2Hu4Y=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=EhywDeIODqslEDLoDwMVItaKeUbZGEQO491Yk8sprkPoWya9a6lJJXZ7a/juHVCSK 9d4PGfpNSa24Boiri2r+fxlA38JTTU16btsB5rkJmk4315f71wrg7kXoR/hp/FK8cQ TmAt8dEOFpSA6HkfIvrF0MC38ejFWtj+QefkjlEnYn56R5PWxc68ubjxgH20Q/83vC 0BHYL4P8lrGZ4xtOO1QCiN4eAsQE2CtVEwGU2UJY8tI9534Gpe0JixmjlwMumFOfBh Y7KfhzUkEIiVU75mAljkQJQK2n+SLjfgcVBOoL0y+DMGYFtIDkk2tSsQ/6nrLpHM3/ 0PGVO63rUnqtQ== Received: from fedora-21.home (unknown [100.64.0.11]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange secp256r1 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: bbrezillon) by bali.collaboradmins.com (Postfix) with ESMTPSA id 4CF2517E0894; Mon, 14 Sep 2026 11:39:52 +0200 (CEST) Date: Mon, 14 Sep 2026 11:39:46 +0200 From: Boris Brezillon To: =?UTF-8?B?QWRyacOhbg==?= Larumbe Cc: Rob Herring , Steven Price , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Faith Ekstrand , "Marty E. Plummer" , Tomeu Vizoso , Eric Anholt , Alyssa Rosenzweig , Robin Murphy , Philipp Zabel , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Collabora Kernel Team , Neil Armstrong Subject: Re: [PATCH v9 10/16] drm/panfrost: Add debugfs knob for manually triggering a GPU reset Message-ID: <20260914113946.69936104@fedora-21.home> In-Reply-To: <20260912-claude-fixes-v9-10-e588feaa61ef@collabora.com> References: <20260912-claude-fixes-v9-0-e588feaa61ef@collabora.com> <20260912-claude-fixes-v9-10-e588feaa61ef@collabora.com> Organization: Collabora X-Mailer: Claws Mail 4.4.0 (GTK 3.24.52; x86_64-redhat-linux-gnu) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable On Sat, 12 Sep 2026 00:28:11 +0100 Adri=C3=A1n Larumbe wrote: > This will be of great help when testing potential races between the GPU > reset sequence and other parts of the code accessing HW registers. >=20 > Signed-off-by: Adri=C3=A1n Larumbe Reviewed-by: Boris Brezillon One comment below. > --- > drivers/gpu/drm/panfrost/panfrost_device.c | 37 ++++++++++++++++++++++++= ++++++ > 1 file changed, 37 insertions(+) >=20 > diff --git a/drivers/gpu/drm/panfrost/panfrost_device.c b/drivers/gpu/drm= /panfrost/panfrost_device.c > index d75566a45392..0aee1d87a7ab 100644 > --- a/drivers/gpu/drm/panfrost/panfrost_device.c > +++ b/drivers/gpu/drm/panfrost/panfrost_device.c > @@ -2,6 +2,7 @@ > /* Copyright 2018 Marty E. Plummer */ > /* Copyright 2019 Linaro, Ltd, Rob Herring */ > =20 > +#include > #include > #include > #include > @@ -583,9 +584,45 @@ EXPORT_GPL_DEV_PM_OPS(panfrost_pm_ops) =3D { > }; > =20 > #ifdef CONFIG_DEBUG_FS > +static int reset_get(void *data, u64 *val) > +{ > + struct panfrost_device *pfdev =3D > + container_of(data, struct panfrost_device, base); > + > + *val =3D atomic_read(&pfdev->reset.pending); > + return 0; > +} > + > +static int reset_set(void *data, u64 val) > +{ > + struct panfrost_device *pfdev =3D > + container_of(data, struct panfrost_device, base); > + int ret =3D pm_runtime_get_if_active(pfdev->base.dev); > + > + if (ret) { > + panfrost_device_schedule_reset(pfdev); It feels weird to schedule a reset if the device is suspended, because a suspend/resume cycle already acts as a reset. Any particular reason you'd want to do that? If not, I'd suggest going for: if (ret <=3D 0) return ret; panfrost_device_schedule_reset(pfdev); pm_runtime_put(pfdev->base.dev); return 0; > + flush_work(&pfdev->reset.work); > + if (ret > 0) > + pm_runtime_put(pfdev->base.dev); > + } > + > + return 0; > +} > + > +DEFINE_DEBUGFS_ATTRIBUTE(panfrost_reset_debugfs_fops, > + reset_get, reset_set, > + "0x%08llx\n"); > + > +static void panfrost_reset_debugfs_init(struct drm_minor *minor) > +{ > + debugfs_create_file("reset", 0600, minor->debugfs_root, > + minor->dev, &panfrost_reset_debugfs_fops); > +} > + > void panfrost_device_debugfs_init(struct drm_minor *minor) > { > panfrost_gem_debugfs_init(minor); > panfrost_sched_debugfs_init(minor); > + panfrost_reset_debugfs_init(minor); > } > #endif // CONFIG_DEBUG_FS >=20