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Mon, 14 Sep 2026 05:53:28 -0700 (PDT) Received: from GLaDOS.station ([187.14.102.91]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49e60acff8bsm320954365e9.9.2026.09.14.05.53.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Sep 2026 05:53:27 -0700 (PDT) From: Stefano Radaelli X-Google-Original-From: Stefano Radaelli To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: pierluigi.p@variscite.com, Stefano Radaelli , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Natasha Kovalenko Subject: [PATCH v1 1/1] arm64: dts: imx95-var-dart-sonata: correct UART8 header pins Date: Mon, 14 Sep 2026 14:53:11 +0200 Message-ID: <20260914125311.8354-1-stefano.r@variscite.com> X-Mailer: git-send-email 2.47.3 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Stefano Radaelli Correct the UART8 header reference from J12 to J6 on the DART-MX95 Sonata carrier board. This is a documentation-only fix and does not change the hardware configuration. Co-developed-by: Natasha Kovalenko Signed-off-by: Natasha Kovalenko Signed-off-by: Stefano Radaelli --- arch/arm64/boot/dts/freescale/imx95-var-dart-sonata.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx95-var-dart-sonata.dts b/arch/arm64/boot/dts/freescale/imx95-var-dart-sonata.dts index 3479abc25df2..9344a0d99418 100644 --- a/arch/arm64/boot/dts/freescale/imx95-var-dart-sonata.dts +++ b/arch/arm64/boot/dts/freescale/imx95-var-dart-sonata.dts @@ -336,7 +336,7 @@ &lpuart1 { status = "okay"; }; -/* Header (J12.4, J12.6) */ +/* Header (J6.4, J6.6) */ &lpuart8 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart8>; -- 2.47.3