From: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
To: <linux-kernel@vger.kernel.org>, <iommu@lists.linux.dev>,
<joro@8bytes.org>, <jgg@nvidia.com>
Cc: <yi.l.liu@intel.com>, <kevin.tian@intel.com>,
<nicolinc@nvidia.com>, <vasant.hegde@amd.com>,
<jon.grimm@amd.com>, <santosh.shukla@amd.com>, <Sairaj.K@amd.com>,
<jay.chen@amd.com>, <Ming.Shu@amd.com>, <SooJin.Tan@amd.com>,
<wvw@google.com>, <wnliu@google.com>, <dantuluris@google.com>,
<chriscli@google.com>, <kpsingh@google.com>,
<alejandro.j.jimenez@oracle.com>, <joao.m.martins@oracle.com>,
<guanghuifeng@linux.alibaba.com>,
Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Subject: [PATCH v5 18/24] iommu/amd: Init and clear vIOMMU DevID and DomID maps
Date: Mon, 14 Sep 2026 18:47:44 +0000 [thread overview]
Message-ID: <20260914184750.222939-19-suravee.suthikulpanit@amd.com> (raw)
In-Reply-To: <20260914184750.222939-1-suravee.suthikulpanit@amd.com>
Before using a vIOMMU instance, prefill the mapping tables so hardware
never sees an unknown guest ID. Map every gdom_id to the nest parent
domain ID, and write every gdev_id with hdev_id 0. Init cannot be
scoped to IDs in use; INVALIDATE_IOMMU_ALL walks the HW table.
Yield vfctrl_lock every 256 doorbells so the 128K MMIO loop can
resched. Attach cannot run until viommu->ops is set after init_one().
On destroy, drain CONTROL0/CONTROL1 WRITE and unmap. Do not rewrite
the full tables: that would start 128K DMA writes into pages about
to be freed. vDevice destroy and nested_domain_free already restored
idle entries.
Skip VFCTRL access when CONTROL_CMDBUF_EN is already clear, matching
viommu_priv_unmap_free() on the same uninit_one() path.
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
---
drivers/iommu/amd/viommu.c | 90 ++++++++++++++++++++++++++++++++++++++
1 file changed, 90 insertions(+)
diff --git a/drivers/iommu/amd/viommu.c b/drivers/iommu/amd/viommu.c
index 7521f470e5d4..e0c5e79cf795 100644
--- a/drivers/iommu/amd/viommu.c
+++ b/drivers/iommu/amd/viommu.c
@@ -7,6 +7,7 @@
#define dev_fmt(fmt) pr_fmt(fmt)
#include <linux/delay.h>
+#include <linux/sched.h>
#include <linux/iommu.h>
#include <linux/iommufd.h>
#include <uapi/linux/iommufd.h>
@@ -447,6 +448,8 @@ static void __maybe_unused free_private_vm_region(struct amd_iommu *iommu, u64 *
#define DEVID_ENTRY_WRITE BIT_ULL(63)
#define DEVID_ENTRY_VALID BIT_ULL(0)
+#define VIOMMU_VFCTRL_PREFILL_RESCHED 256
+
/*
* CONTROL0/CONTROL1 bit 63 (WRITE) is a doorbell: hardware copies one
* entry into the IPA-backed table and clears WRITE when that DMA write
@@ -559,10 +562,95 @@ void amd_viommu_domain_id_update(struct amd_iommu_viommu *aviommu,
mutex_unlock(&aviommu->vfctrl_lock);
}
+static bool viommu_vfctrl_ready(struct amd_iommu *iommu)
+{
+ return iommu->vfctrl_base && viommu_cmdbuf_enabled(iommu);
+}
+
+/*
+ * Drain outstanding CONTROL0/CONTROL1 table DMA before the IPA pages
+ * are unmapped and freed. Do not rewrite 0..0xFFFF: vDevice destroy
+ * and nested_domain_free already restored idle entries, and a full
+ * walk would start 128K new DMA writes into pages about to be freed.
+ *
+ * Skip after disable_iommus(): CMDBUF_EN is already clear, matching
+ * viommu_priv_unmap_free() which skips IOTLB invalidation.
+ */
+static void viommu_drain_mapping(struct amd_iommu *iommu,
+ struct amd_iommu_viommu *aviommu)
+{
+ u16 gid = aviommu->gid;
+
+ if (!viommu_vfctrl_ready(iommu))
+ return;
+
+ mutex_lock(&aviommu->vfctrl_lock);
+ vfctrl_wait_write_clear(iommu, gid,
+ VIOMMU_VFCTRL_GUEST_DID_MAP_CONTROL0_OFFSET);
+ vfctrl_wait_write_clear(iommu, gid,
+ VIOMMU_VFCTRL_GUEST_DID_MAP_CONTROL1_OFFSET);
+ mutex_unlock(&aviommu->vfctrl_lock);
+}
+
+static void viommu_prefill_resched(struct amd_iommu_viommu *aviommu, int i)
+{
+ lockdep_assert_held(&aviommu->vfctrl_lock);
+
+ if ((i & (VIOMMU_VFCTRL_PREFILL_RESCHED - 1)) !=
+ VIOMMU_VFCTRL_PREFILL_RESCHED - 1)
+ return;
+
+ mutex_unlock(&aviommu->vfctrl_lock);
+ cond_resched();
+ mutex_lock(&aviommu->vfctrl_lock);
+}
+
+/*
+ * Prefill every guest ID so hardware never sees an unknown mapping.
+ * Map all gdom_id to the nest parent domain ID, and all gdev_id with
+ * hdev_id 0. Cannot be scoped to IDs in use: none exist yet, and
+ * INVALIDATE_IOMMU_ALL walks the HW table.
+ *
+ * Drop vfctrl_lock every VIOMMU_VFCTRL_PREFILL_RESCHED doorbells so
+ * the 128K MMIO loop can yield. Safe on init: vDevice/nested attach
+ * cannot run until viommu->ops is published after init_one().
+ */
+static void viommu_prefill_mapping(struct amd_iommu *iommu,
+ struct amd_iommu_viommu *aviommu)
+{
+ int i;
+ u16 gid = aviommu->gid;
+
+ if (!viommu_vfctrl_ready(iommu))
+ return;
+
+ mutex_lock(&aviommu->vfctrl_lock);
+ if (aviommu->domid_table) {
+ for (i = 0; i <= VIOMMU_MAX_GDOMID; i++) {
+ domain_id_update_unlocked(iommu, gid,
+ aviommu->parent->id, i);
+ viommu_prefill_resched(aviommu, i);
+ }
+ }
+
+ if (aviommu->devid_table) {
+ for (i = 0; i <= VIOMMU_MAX_GDEVID; i++) {
+ set_device_mapping_unlocked(iommu, gid, 0, i);
+ viommu_prefill_resched(aviommu, i);
+ }
+ }
+ mutex_unlock(&aviommu->vfctrl_lock);
+}
+
void amd_viommu_uninit_one(struct amd_iommu *iommu, struct amd_iommu_viommu *aviommu)
{
pr_debug("%s: gid=%u\n", __func__, aviommu->gid);
+ /*
+ * Wait until CONTROL0/CONTROL1 table DMA has retired before
+ * the backing pages are unmapped and freed.
+ */
+ viommu_drain_mapping(iommu, aviommu);
free_private_vm_region(iommu, &aviommu->devid_table,
VIOMMU_DEVID_MAPPING_BASE,
VIOMMU_DEVID_MAPPING_ENTRY_SIZE,
@@ -591,6 +679,8 @@ int amd_viommu_init_one(struct amd_iommu *iommu, struct amd_iommu_viommu *viommu
if (ret)
goto err_out;
+ viommu_prefill_mapping(iommu, viommu);
+
return 0;
err_out:
amd_viommu_uninit_one(iommu, viommu);
--
2.34.1
next prev parent reply other threads:[~2026-09-14 18:50 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-14 18:47 [PATCH v5 00/24] iommu/amd: Introduce AMD Hardware-accelerated Virtualized IOMMU (vIOMMU) Support Suravee Suthikulpanit
2026-09-14 18:47 ` [PATCH v5 01/24] iommu/amd: Introduce vIOMMU-specific events and event Suravee Suthikulpanit
2026-09-14 18:47 ` [PATCH v5 02/24] iommu/amd: Introduce EVENT_TYPE_GUEST_EVENT_FAULT Suravee Suthikulpanit
2026-09-14 18:47 ` [PATCH v5 03/24] iommu/amd: Detect and initialize AMD vIOMMU feature Suravee Suthikulpanit
2026-09-14 18:47 ` [PATCH v5 04/24] iommu/amd: Introduce IOMMUFD vIOMMU support for AMD Suravee Suthikulpanit
2026-09-14 18:47 ` [PATCH v5 05/24] iommu/amd: Allocate Guest IDs for IOMMUFD vIOMMU instances Suravee Suthikulpanit
2026-09-14 18:47 ` [PATCH v5 06/24] iommu/amd: Map vIOMMU VF and VF Control MMIO BARs Suravee Suthikulpanit
2026-09-14 18:47 ` [PATCH v5 07/24] iommu/amd: Add support for AMD vIOMMU VF MMIO region Suravee Suthikulpanit
2026-09-14 18:47 ` [PATCH v5 08/24] iommu/amd: Introduce Reset vMMIO Command Suravee Suthikulpanit
2026-09-19 15:11 ` guanghuifeng
2026-09-14 18:47 ` [PATCH v5 09/24] iommu/amd: Introduce and map vIOMMU private IPA region Suravee Suthikulpanit
2026-09-14 18:47 ` [PATCH v5 10/24] iommu/amd: Pass iommu to device_flush_dte() Suravee Suthikulpanit
2026-09-14 18:47 ` [PATCH v5 11/24] iommu/amd: Pass iommu and devid to amd_iommu_make_clear_dte() Suravee Suthikulpanit
2026-09-14 18:47 ` [PATCH v5 12/24] iommu/amd: Store per-segment iommu_dev_data in an xarray Suravee Suthikulpanit
2026-09-14 18:47 ` [PATCH v5 13/24] iommu/amd: Program IOMMU DTE with the private IPA domain Suravee Suthikulpanit
2026-09-19 15:26 ` guanghuifeng
2026-09-14 18:47 ` [PATCH v5 14/24] iommu/amd: Add per-VM private IPA alloc/map helpers Suravee Suthikulpanit
2026-09-14 18:47 ` [PATCH v5 15/24] iommu/amd: Add helper functions to manage DevID / DomID mapping tables Suravee Suthikulpanit
2026-09-14 18:47 ` [PATCH v5 16/24] iommu/amd: Add IOMMUFD vDevice and DevID mapping Suravee Suthikulpanit
2026-09-14 18:47 ` [PATCH v5 17/24] iommu/amd: Program nested DTE and DomID map on attach Suravee Suthikulpanit
2026-09-14 18:47 ` Suravee Suthikulpanit [this message]
2026-09-14 18:47 ` [PATCH v5 19/24] iommu/amd: Add per-segment translate device ID pool Suravee Suthikulpanit
2026-09-14 18:47 ` [PATCH v5 20/24] iommu/amd: Reserve translate-device-id for PCI requestor aliases Suravee Suthikulpanit
2026-09-14 18:47 ` [PATCH v5 21/24] iommu/amd: Add translation DTE and VFctrl TransDevID helpers Suravee Suthikulpanit
2026-09-14 18:47 ` [PATCH v5 22/24] iommu/amd: Add translate-device-id alloc/free with vIOMMU owner Suravee Suthikulpanit
2026-09-14 18:47 ` [PATCH v5 23/24] iommu/amd: Assign per-vIOMMU translate device ID Suravee Suthikulpanit
2026-09-14 18:47 ` [PATCH v5 24/24] iommu/amd: Relocate vIOMMU translate-device-id on PCI reserve Suravee Suthikulpanit
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