From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6F4F73630AC; Mon, 14 Sep 2026 22:47:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789426024; cv=none; b=tJXUXpZAhYTSwpUREwfpJ0d51XeMO+xXr7Y4SPlwm7gFW7letsz2rT8eIIFRt4U0W4gMPmfwPdFgWU5BV1r3k4l/aNSQSAE7hsiMfP8rnIfzoVPzBmqGZFPWsl5f/3xpQDDnaM2YE+0NhrUc6xYG4HlX6FO6/IcJN2yFJAUYa5U= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789426024; c=relaxed/simple; bh=yTOa3uyq03oDEB7rUBOaYUoZhV+lRryyQaR/6S5HJi4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=TVf0M+3QTnHXA20xM23M8Mkv1ti2B6euiwFi1aaSsPDeW7wipQsAvZtazp2wQ7148EIkjXT7COWCFBcaqmIGEGRZ6o61+McrWxVhZ0M+C8L1aftUQYaxIGsaGBO6gpl+q+PIai2nCoz656CyNE2+UFKZoeC/SuufotCSNwFGzr4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=SUqaZ3Sb; arc=none smtp.client-ip=198.175.65.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="SUqaZ3Sb" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1789426022; x=1820962022; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=yTOa3uyq03oDEB7rUBOaYUoZhV+lRryyQaR/6S5HJi4=; b=SUqaZ3Sb7x+P3tn3FWJ6rfm93o9AHDExU4gGRoQ5U7QuLPDXPdZno0Iw Hf0SbH1wJxr3hZhyjun9Vx0HOMCVRe3KvT6H7EGGrwQol26xH+K5ubhwv pwrffLOiMjRArnaPDSKIJjveTw2EgJU/AgWKgut699W62C/bQnG6JGmWs uIaSm53puseAnU5mfukbxB7ExESdOmXpTLNp+yGn242NsHeEW2Vg/gABC DDmcb5tosWkQdJKO4AHcQLa9pX//1B9/PTOqBhpb5voJC8hKJA/IGPtpm FNW78vmMsR2rYunkv3muMHbNFj3ct+Tsb3Slh2upzH/KsNeM56EFkRmmu g==; X-CSE-ConnectionGUID: 5qcDf/m/REOvMMsEGN2BFg== X-CSE-MsgGUID: hpfuf4dDS/ere00ElShxmg== X-IronPort-AV: E=McAfee;i="6800,10657,11905"; a="93483220" X-IronPort-AV: E=Sophos;i="6.27,103,1787036400"; d="scan'208";a="93483220" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Sep 2026 15:47:02 -0700 X-CSE-ConnectionGUID: NuA3RJn7T+OBm4G8orW0Nw== X-CSE-MsgGUID: jqrWVrM2SSq3TJVK3ZX7hw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.27,103,1787036400"; d="scan'208";a="268480097" Received: from khuang2-desk.gar.corp.intel.com (HELO tfalcon-desk.attlocal.net) ([10.124.223.56]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Sep 2026 15:47:01 -0700 From: Thomas Falcon To: Dapeng Mi Cc: linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark Subject: [PATCH v9 2/6] perf mem: Add support for printing PERF_MEM_LVLNUM_L0 Date: Mon, 14 Sep 2026 17:46:46 -0500 Message-ID: <20260914224650.52982-3-thomas.falcon@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260914224650.52982-1-thomas.falcon@intel.com> References: <20260914224650.52982-1-thomas.falcon@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Dapeng Mi Add support for printing PERF_MEM_LVLNUM_L0 in perf mem report. The L0 cache is newly added a small piece of cache which is the closest, lowest-latency memory cache tied directly to the execution pipeline. The table "Table 9-4. Data Source Field Encodings for Panther Cove and Coyote Cove Microarchitectures" in the ISE doc chapter "9.2.1 Panther Cove and Coyote Cove Microarchitectures Memory Auxiliary Field Layout"[1] indicates the code "01H" means the "L0 Hit - Minimal latency core cache hit. This request was satisfied by the L0 data cache." [1]: https://www.intel.com/content/www/us/en/content-details/922690/intel-architecture-instruction-set-extensions-programming-reference.html Assisted-by: Sashiko:gemini-3.1-pro-preview Reviewed-by: Dapeng Mi Reviewed-by: Ian Rogers Reviewed-by: Namhyung Kim Signed-off-by: Dapeng Mi Co-developed-by: Thomas Falcon Signed-off-by: Thomas Falcon --- v8: Updated developer tags v3: Included more information about the L0 cache in the commit message. --- tools/perf/Documentation/perf-record.txt | 2 +- tools/perf/util/bpf-filter.l | 1 + tools/perf/util/mem-events.c | 5 +++++ tools/perf/util/mem-events.h | 1 + 4 files changed, 8 insertions(+), 1 deletion(-) diff --git a/tools/perf/Documentation/perf-record.txt b/tools/perf/Documentation/perf-record.txt index 2c6510c5a87b..17030ecac577 100644 --- a/tools/perf/Documentation/perf-record.txt +++ b/tools/perf/Documentation/perf-record.txt @@ -212,7 +212,7 @@ OPTIONS The can be one of: (for any term) na, load, store, pfetch, exec (for mem_op) - l1, l2, l3, l4, cxl, io, any_cache, lfb, ram, pmem (for mem_lvl) + l0, l1, l2, l3, l4, cxl, io, any_cache, lfb, ram, pmem (for mem_lvl) na, none, hit, miss, hitm, fwd, peer (for mem_snoop) remote (for mem_remote) na, locked (for mem_locked) diff --git a/tools/perf/util/bpf-filter.l b/tools/perf/util/bpf-filter.l index 6aa65ade3385..1be9df6550fc 100644 --- a/tools/perf/util/bpf-filter.l +++ b/tools/perf/util/bpf-filter.l @@ -131,6 +131,7 @@ store { return constant(PERF_MEM_OP_STORE); } pfetch { return constant(PERF_MEM_OP_PFETCH); } exec { return constant(PERF_MEM_OP_EXEC); } +l0 { return constant(PERF_MEM_LVLNUM_L0); } l1 { return constant(PERF_MEM_LVLNUM_L1); } l2 { return constant(PERF_MEM_LVLNUM_L2); } l3 { return constant(PERF_MEM_LVLNUM_L3); } diff --git a/tools/perf/util/mem-events.c b/tools/perf/util/mem-events.c index 4e490f9cd348..4fd48fd20055 100644 --- a/tools/perf/util/mem-events.c +++ b/tools/perf/util/mem-events.c @@ -391,6 +391,7 @@ static const char * const mem_lvlnum[] = { [PERF_MEM_LVLNUM_L4] = "L4", [PERF_MEM_LVLNUM_L2_MHB] = "L2 MHB", [PERF_MEM_LVLNUM_MSC] = "Memory-side Cache", + [PERF_MEM_LVLNUM_L0] = "L0", [PERF_MEM_LVLNUM_UNC] = "Uncached", [PERF_MEM_LVLNUM_CXL] = "CXL", [PERF_MEM_LVLNUM_IO] = "I/O", @@ -831,6 +832,8 @@ int mem_stat_index(const enum mem_stat_type mst, const u64 val) } case PERF_MEM_STAT_CACHE: switch (src.mem_lvl_num) { + case PERF_MEM_LVLNUM_L0: + return MEM_STAT_CACHE_L0; case PERF_MEM_LVLNUM_L1: return MEM_STAT_CACHE_L1; case PERF_MEM_LVLNUM_L2: @@ -915,6 +918,8 @@ const char *mem_stat_name(const enum mem_stat_type mst, const int idx) } case PERF_MEM_STAT_CACHE: switch (idx) { + case MEM_STAT_CACHE_L0: + return "L0"; case MEM_STAT_CACHE_L1: return "L1"; case MEM_STAT_CACHE_L2: diff --git a/tools/perf/util/mem-events.h b/tools/perf/util/mem-events.h index 5b98076904b0..daa22748f9fe 100644 --- a/tools/perf/util/mem-events.h +++ b/tools/perf/util/mem-events.h @@ -109,6 +109,7 @@ enum mem_stat_op { }; enum mem_stat_cache { + MEM_STAT_CACHE_L0, MEM_STAT_CACHE_L1, MEM_STAT_CACHE_L2, MEM_STAT_CACHE_L3, -- 2.55.0