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Mon, 14 Sep 2026 23:00:43 +0000 From: Ali Rouhi To: "netdev@vger.kernel.org" CC: Ali Rouhi , "jiri@resnulli.us" , "vadim.fedorenko@linux.dev" , "arkadiusz.kubalewski@intel.com" , "ivecera@redhat.com" , "robh@kernel.org" , "krzk+dt@kernel.org" , "conor+dt@kernel.org" , "cjubran@nvidia.com" , "pabeni@redhat.com" , "Oleg.Zadorozhnyi@devoxsoftware.com" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH net-next v8 11/15] dpll: sit9531x: add support to get and set esync on pins Thread-Topic: [PATCH net-next v8 11/15] dpll: sit9531x: add support to get and set esync on pins Thread-Index: AQHdOyOwbuY3GSPEK0aUf9+si1JKiLbEqYqAgAoZ2oA= Date: Mon, 14 Sep 2026 23:00:39 +0000 Message-ID: <20260914230034.63861-10-arouhi@sitime.com> References: <178887152134.219967.16181634650893462486@kernel.org> In-Reply-To: <178887152134.219967.16181634650893462486@kernel.org> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=sitime.com; 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Replies inline. The esync path was substantially=0A= reworked in v9, which resolves most of the points below at once.=0A= =0A= > Is the embedded sync frequency here the marker rate or the carrier rate?= =0A= =0A= v8 conflated the two. v9 implements the uAPI=0A= semantics: the supported embedded-sync rate is the 1 Hz marker, the carrier= =0A= stays the pin's separately configured frequency, and the changelog now=0A= describes exactly what the code does.=0A= =0A= > Where is the pin's previous output rate saved so this path can restore it= ?=0A= =0A= Fixed in v9: the pre-esync rate is saved when esync is enabled and=0A= restored when it is disabled, so an enable/disable cycle returns the pin to= =0A= the rate userspace configured.=0A= =0A= > What happens if the second or third step here fails?=0A= =0A= Fixed in v9: a failure after the first committed step unwinds the=0A= pulse-control write, and the cached esync state is only updated when the=0A= whole sequence succeeded, so the reported state cannot claim "disabled" for= a=0A= pin whose carrier was already changed.=0A= =0A= > Can dpin->esync_freq go stale here? [frequency_set / disable do not clea= r=0A= > it]=0A= =0A= Closed in v9 from the other side: a frequency_set on a pin with esync=0A= enabled is rejected with -EBUSY and an extack asking to disable esync first= ,=0A= so the cached esync state and the carrier can no longer diverge through tha= t=0A= path.=0A= =0A= > Should esync->pulse be reported as 0 when esync->freq is 0?=0A= =0A= Yes -- fixed in v9, matching ice and zl3073x: both fields read 0 in=0A= the disabled case.=0A= =0A= > it looks like one constant is being used both as a uAPI percentage and as= a=0A= > raw register value. Which of the two is it? [and: full-byte write]=0A= =0A= For the single supported configuration (1 Hz marker) the=0A= PROG0 pulse-control value that produces the emitted marker corresponds to t= he=0A= 50 percent duty the getter advertises, which is why one literal appears in= =0A= both roles; the v9 comment states this explicitly. PROG0 in this mode is= =0A= wholly the pulse control byte, so the full-byte write does not clobber=0A= unrelated fields; this was verified on hardware (SiT95317 evaluation board)= =0A= by checking the marker against the blob-programmed configuration.=0A= =0A= > could this byte be written inside the window sit9531x_output_freq_set()= =0A= > already opens?=0A= =0A= It could, and it is a good micro-optimisation, but merging the two=0A= windows couples the esync path into the frequency helper's error handling f= or=0A= a saving of one commit cycle on a rare configuration operation. We kept th= e=0A= operations separate for clarity; happy to revisit if the extra commit cycle= =0A= turns out to matter in practice.=0A= =0A= > The comment says this byte applies in SYSREF / SYNCB modes. The new esyn= c=0A= > path does not select either mode, so does the write take effect at all [.= ..]?=0A= =0A= The outputs wired for esync on our reference board=0A= are configured by the NVM blob into the mode where the pulse byte applies;= =0A= the driver's esync-control DT flag is what marks exactly those outputs, so= =0A= the path is only reachable where the write takes effect. This is=0A= bench-verified on the SiT95317 board.=0A=