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Replies inline.=0A= =0A= > does the banner describe the wrong polarity? It says MASK+STATE are set = to=0A= > mute, while the body sets MASK and clears STATE=0A= =0A= Fixed in v9 -- the banner now says "sets MASK and clears STATE",=0A= matching the register description and the code.=0A= =0A= > Can a partial register sequence here leave sitdev->out[index].enabled=0A= > permanently disagreeing with the hardware?=0A= =0A= v9 re-reads the force/state pair after a failed=0A= sequence and records what the hardware actually holds, so the cached flag= =0A= cannot disagree with the chip for the life of the binding.=0A= =0A= > Does this read past sitdev->out[] for the internal INTSYNC source pin?=0A= =0A= Resolved by the v9 registration restructure: the=0A= INTSYNC source pin is registered only together with its dedicated ops table= =0A= (the inter-PLL sync patch), so no commit dispatches it to the generic outpu= t=0A= getter and the out-of-bounds read is gone at every bisect point.=0A=